Jul 2018 – Jan 2023 · 4 yrs 6 mos · Bengaluru, Karnataka, India

• ROLE: Lead for Physical Design Implementation and P&R closure for SPRMCC and
• EMRSPMCC and ICXD subfcs and some initiatives of DSO and AI capabilities of P&R for
• fusion compiler backend (Technology: Intel 10 and Intel 7)
• Leading 3 subfcs in soc (Around 19 partitions) for overall convergence with team of 5
• people
• Leading and mentoring junior employees and interfacing with front end design team to
• improve RTL and design quality
• Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS
• Implementation (Place and Route, static timing) using industry standard (synopsys) EDA
• tools
• Physical design knowledge, from netlist handoff to GDS tape out including floor planning,
• place and route, clock tree synthesis with timing closure
• Expert in developing Synopsys ICC based flows to drive block PnR, Timing Closure and
• Final sign off
• Provide technical direction, coaching, and mentoring to employees on your team and others
• when necessary to achieve successful project outcomes
• Leading DSO related activities for better PPA and some AI related capabilities with fusion
• compiler

Jul 2016 – Jan 2018 · 1 yr 6 mos · Bengaluru, Karnataka, India

• I have experienced on Interface IO (IIO) subsystem partition, memory bundle control partition convergence (having high gate count, multi power domains and with more then 6 no of macros) having high complexity, CHA and also on server soc partitions convergence.
• Leading team of 5 people and handling multiple partitions
• Working experience on 14nm, 10nm and INTEL7 technology node
• Tape out experience : IIO and CHA subsystem, 10nm server SOC ( 4 tape-out experience)
• My responsibilities include:
• 1. CHA and IIO partitions (14nm):
• RTL to netlist generation using Design Compiler:
• Performing synthesis and providing valuable feedback on quality of RTL and timing specs and consumability of the same to downstream flows.
• Placement and Route using IC Compiler:
• experimenting and coming up with placement strategies for skewed partitions
• Coming up with routing strategies to minimize slack and converge timing
• Primetime Analysis:
• Timing analysis using primetime and verifying different timing paths and generating eco to fix paths
• Manual ECO fixing
• Worked on manual eco fixing according to design requirement
• Debugging different LEC issue and caliber issues and writing the script to provide solutions
• Horizontal responsibilities:
• Quality checks like LEC, caliber, noise, power analysis
• Worked as a solution provider for SOC partition for LEC and caliber checks
• Constraints checking and validation, Pre-Layout STA
• STA: Static Timing closure/Timing Analysis/Timing fixes
• 2. Icelake and SPR Server SOC (10nm and INTEL7)
• Starting from synthesis to placement and routing, proper CTS latencies building and routing for congestion free design
• primetime analysis till final convergence of SOC and tapeout
• worked on floorplan of SOC also
• Other responsibilities: .
• Testing and flushing out company-specific flows by collaborating with EDA engineers
• Planning component placement in Full Chip for consumption to partition owners

Jan 2016 – Jun 2016 · 5 mos · Bangaon, West Bengal, India

• FinFET Device Characterization and Process Benchmarking for Memory Design
• Worked on optimizing various repeaters stages used in the Cache memory.
• Study of the process technology and benchmarking the process parameters are very important in choosing right technology as well as picking right devices within a given technology.
• A comparative study between two technologies and the devices within a given technology
• Design some parts of the register file design like keeper circuit to keep the voltage level at one particular value and power header design to reduce the leakage power for cache memory .

Jan 2013 – May 2013 · 4 mos · Greater Ahmedabad Area

• Worked on research work related to gamma ray specrometer radiation measurement
• Develop software to measure radiation of gamma rays which will be radiated from the surface of the different planet