Harikrishna Emani

Software Engineer

Bengaluru, Karnataka, India16 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in VLSI and Physical Design.
  • Proven track record in Static Timing Analysis.
  • Strong experience in SoC and ASIC design.
Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in physical design engineering.

Contact

LinkedIn

Skills

Core Skills

VlsiPhysical Design

Other Skills

VHDLStatic Timing AnalysisTiming ClosurePrimetimeLogic SynthesisSoCPlace & RoutePower AnalysisSynopsys PrimetimeCompilersConformal LECRedhawkASICEDAFloorplanning

Experience

16 yrs 2 mos
Total Experience
2 yrs 1 mo
Average Tenure
3 yrs 9 mos
Current Experience

Qualcomm

Sr Staff Engineer

Aug 2022 – Present · 3 yrs 8 mos

VHDLVLSIPhysical DesignStatic Timing AnalysisTiming ClosurePrimetime+14

Barefoot networks

2 roles

SoC Design Engineer

Promoted

Nov 2019 – Aug 2022 · 2 yrs 9 mos · Raleigh, North Carolina, United States

  • RV lead.
  • Integration lead.

Hardware Engineer

Jun 2016 – Sep 2018 · 2 yrs 3 mos · palo alto

Amd

MTS Asic Layout/Physical Design Engineer

Sep 2018 – Nov 2019 · 1 yr 2 mos · santa clara

  • Started working in Full chip Integration team!

Perfect vips

Senior Physical Design Engineer

Nov 2015 – May 2016 · 6 mos · CA

  • Physical Design Flow Automation & support

Synapse design automation inc.

Tech Lead

Jan 2014 – Dec 2015 · 1 yr 11 mos · Santa clara

  • worked in Altera 14nm node chip tape out. Responsible for owner ship of a block and top level prerouting and RDL routing.

Sandisk

Physical Design Engineer

Jul 2013 – Dec 2014 · 1 yr 5 mos · Milpitas,CA

  • Physical design for block level designs with gate counts of 1M+ using the 28nm TSMC HPM process using SOC Encounter and the timing closure in primetime

Wipro technologies

Project Engineer

Aug 2009 – Jan 2013 · 3 yrs 5 mos · Greater Hyderabad Area

  • worked in Synthesis,STA,place and route flow,power analysis and LEC. Exposed to the tools like SOC encounter, primetime,Design compiler, EPS and conformal LEC

Education

amrita school of engineering

Master of Technology (MTech) — VLSI

Jan 2007 – Jan 2009

vignan's engineering college

Bachelor of Technology (BTech)

Jan 2003 – Jan 2007

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