Shilpa R

Software Engineer

Netherlands7 yrs 6 mos experience

Highly Stable

Key Highlights

Expert in PCIe Gen6/Gen7 verification.
Proven track record in 5G modem verification.
Skilled in developing scalable UVM testbenches.

Stackforce AI infers this person is a Semiconductor and Telecommunications verification expert with extensive experience in high-speed interfaces.

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Skills

Core Skills

Universal Verification Methodology (uvm)SystemverilogFunctional VerificationAssembly LanguageProcessor Verification5g

Other Skills

Semiconductor IndustryProblem SolvingUVMPCIeHigh-speed interfaceRegression DebugVerification EnvironmentTiming ModelsVerification MethodologiesC ProgrammingObject-Oriented Programming (OOP)Very-Large-Scale Integration (VLSI)C (Programming Language)VerilogLinux

About

Verification Engineer with 7 years of extensive experience in high-speed interface and communication system verification. Specialized in PCIe Gen6/Gen7 Receiver Application Layer verification, including TLP parsing, flow control, and protocol-level checks. Proven expertise in 5G modem verification (both UE and base station), covering sub-blocks such as Scrambler, MIMO, Pre-Digital Front-End, and Bit Rate Processing using SystemVerilog (SV) and Universal Verification Methodology (UVM). Skilled in verifying complex digital systems, including Ethernet and Eframer blocks, and performing processor-level verification with assembly programming.Well-versed in the complete verification lifecycle—from planning to closure, with hands-on experience developing scalable test environments and UVM testbenches. Proficient in C programming for embedded verification and driven by a focus on delivering efficient, high-quality results for cutting-edge communication and interface designs.

Experience

7 yrs 6 mos

Total Experience

3 yrs 1 mo

Average Tenure

1 yr 3 mos

Current Experience

Synopsys inc

Staff Engineer

Feb 2025 – Present · 1 yr 3 mos · Bangalore Urban, Karnataka, India · On-site

Worked on verification of the PCIe Receiver Application Layer for Gen6 and Gen7, with a focus on high-speed interface compliance, transaction-level protocol checks, and flow control mechanisms.
Developing UVM-based testbenches and verification components to validate PCIe features including Unordered I/O (UIO) handling.

Semiconductor IndustryProblem SolvingUniversal Verification Methodology (UVM)SystemVerilog

Nokia

Technical Specialist

Nov 2022 – Jan 2025 · 2 yrs 2 mos · Tampere, Pirkanmaa, Finland

Experienced in end-to-end verification of high-speed communication buffers and interfaces, including 5G Uplink/Downlink Symbol Buffers and Ethernet/Eframer blocks, using SystemVerilog and UVM. Led the complete verification cycle from test planning, testbench development, and corner-case scenario creation to functional and code coverage closure, ensuring strict compliance with design and protocol specifications. Collaborated closely with design teams to debug complex issues, improve verification methodologies, and deliver robust, reusable environments that enhanced test coverage and overall verification efficiency.

Mediatek

3 roles

Staff Engineer

Jun 2022 – Oct 2022 · 4 mos

Led MIPS Processor Verification by extending the existing environment to support five virtual processing elements (up from three).
Developed assembly test cases for core‑level interrupts and exceptions, and updated regression scripts to integrate new features.
Drove regression debug and coverage closure for the Bus Interface Unit (BIU) and Arithmetic Logic Unit (ALU), ensuring robust processor verification.

Semiconductor IndustryProblem SolvingAssembly LanguageProcessor Verification

Senior Design Verification Engineer

Jul 2020 – May 2022 · 1 yr 10 mos

Contributed to 5G Multimode Modem Verification (Sub‑6GHz + mmWave), gaining deep understanding of modem architecture and design specs.
Verified the Modem Transmit Subsystem Partition Wrap by building timing models, monitors, and scoreboards.
Calculated and validated clock frequencies to meet mmWave specification requirements.

Design Verification Engineer

Jul 2018 – Jun 2020 · 1 yr 11 mos

Worked on 5G Sub‑6GHz Modem Verification, developing environments for Multi‑Component Carrier Bit Rate Processing Blocks with timing checkers and constraints.
Created a C tool to parse software binaries and auto‑generate SystemVerilog files for use in DV bring‑up and simulation.
Implemented input verification checks and verified Single‑Component Carrier Bit and Symbol Rate Processing Blocks, including monitors, coverage models, and regression debug.