Karishma Singh

Product Engineer

Noida, Uttar Pradesh, India13 yrs 5 mos experience
Highly Stable

Key Highlights

  • Expert in SystemVerilog and UVM methodologies.
  • Proven track record in low-power design and verification.
  • Strong teamwork and communication skills.
Stackforce AI infers this person is a highly skilled engineer in the semiconductor and electronic design automation industry.

Contact

LinkedIn

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)

Other Skills

Gate Level SimulationLow-power DesignFormal VerificationCode Coveragefunctional coverageTeamworkPowerPointMicrosoft WordMicrosoft ExcelMicrosoft Office

Experience

13 yrs 5 mos
Total Experience
3 yrs 8 mos
Average Tenure
1 yr 3 mos
Current Experience

Cadence

4 roles

Principal Product Engineer

Feb 2025 – Present · 1 yr 3 mos

Sr principle product engineer

Promoted

Jan 2025 – Present · 1 yr 4 mos

SystemVerilogGate Level SimulationLow-power DesignFormal VerificationCode Coveragefunctional coverage+1

Lead Product Engineer

Nov 2021 – Feb 2025 · 3 yrs 3 mos

Lead Application Engineer

May 2017 – Nov 2021 · 4 yrs 6 mos

Qualcomm

Lead Engineer

Dec 2016 – Apr 2017 · 4 mos

Cadence design systems

2 roles

Application Engineer

Feb 2014 – Nov 2016 · 2 yrs 9 mos

Intern

Sep 2012 – Jan 2014 · 1 yr 4 mos

  • Job profile --> Application Engineer (Technical Support)

Education

ABES Engg College

Bachelor of Technology (BTech)

Jan 2008 – Jan 2012

Delhi Public School

Jan 2004 – Jan 2008

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