Riya K.

Software Engineer

Bengaluru, Karnataka, India2 yrs 8 mos experience

Key Highlights

Expertise in RTL-to-GDSII implementation and quality checks.
Experience with 3nm automotive SoC design at MediaTek.
Strong foundation in VLSI Design from NIT Jalandhar.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Synthesis.

Contact

Skills

Core Skills

Physical DesignSynthesisCmos

Other Skills

IntegrationTcl-TkCell characterizationPVT analysisFusion CompilerCheetah FlowPhysical SynthesisLogical SynthesisBlock level QCCoverage ChecksSynthesis and IntegrationElectrical checksTiming ChecksCommunicationElectronic Engineering

About

VLSI professional specializing in Physical Design & Synthesis currently working at Cadence. Experienced in RTL-to-GDSII implementation, logical and physical synthesis, and signoff quality checks across advanced technology nodes. Worked at MediaTek on 3nm automotive SoC design, and gained backend flow experience at Intel through a year-long internship. Hold an MTech in VLSI Design from NIT Jalandhar (2023) and began my career as a Design Apprentice at Semiconductor Laboratory (ISRO, Govt. of India). Strong understanding in RTL-to-GDS flows, timing closure, and quality checks, with a focus on collaboration, innovation, and delivering high-quality design solutions.

Experience

2 yrs 8 mos

Total Experience

2 yrs 2 mos

Average Tenure

6 mos

Current Experience

Cadence

Senior Solutions Engineer

Nov 2025 – Present · 6 mos · Bengaluru, Karnataka, India

Mediatek

VLSI Engineer

Aug 2023 – Oct 2025 · 2 yrs 2 mos · Bengaluru, Karnataka, India · On-site

Physical Design Engineer
Handled PnR for multi-power-domain block with 110 Macros to achieve optimal utilization and timing.
Power Planning for multi-power domain blocks, ensuring efficient power distribution across VA levels.
Worked with UPF for defining power intent and managing level shifters, isolation cells, across domains.
Remediated Physical Verification rule violations in PG mesh to ensure power integrity.
Automated tasks through script development, enhancing workflow and reducing manual efforts.
Applied various placement strategies to achieve optimal PPA & improved data transmission integrity.
Refined placement to ensure proper cell alignment, fill coverage, and elimination of gaps and overlaps.
Synthesis & Integration engineer
Verified DEF for high-quality PnR outputs and executed comprehensive checks (LEC, ERC, DRC, ATPG).
Responsible for comprehensive block-level synthesis and quality checks for digital block designs.
Managed top-level QC processes, integrating complex hierarchical designs to meet optimal results.
Performed flattened QC to ensure seamless integration of sub-designs as single-level design.
Collaborated with the DFT team to integrate DFT scan plans, enhancing test coverage and reliability.
Verified the quality of DEF (Design Exchange Format) generated by PnR (Place and Route) tools.
Executed comprehensive quality checks on synthesized netlists, including LEC, CLP, ERC, SDC, clock tree sanity, DRC, DFTV and ATPG.

Physical DesignSynthesisIntegration

Intel corporation

Graduate Technical Intern

Jun 2022 – Jun 2023 · 1 yr · Bengaluru, Karnataka, India

Worked in Physical Design Domain
Implemented APR FC on Cheetah Flow based environment for assigned block.
Handling Congestion ,Timing violations, Shorts ,DRC violations.
Worked with Standard Cell libraries for PPA Analysis.
Parsing and Extracting required data from report files using Python and TCL
Working with Fusion compiler and Flow Tracer tools
Used SED,AWK, grep and many Unix commands for data processing
Projects:
Project 1 : Standard Cell Library Analysis
Conducted analysis and characterization of cell delays across various PVT (Process, Voltage, Temperature)
conditions and drive strength variations.
Evaluated and optimized cell performance and power consumption for different VT types
Analysis of On Chip Variations and Temperature inversion at lower nodes
Project 2 : Executed assigned blocks using Fusion Compiler
Implemented APR FC on Cheetah Flow based environment for assigned block
Blocking and unblocking Standard cells based on Qor reports
Ensuring efficient placement and routing for optimal performance.

Tcl-TkPhysical Design

Scl | semi-conductor laboratory

Project Apprentice

Jan 2020 – Jun 2020 · 5 mos · Sahibzada Ajit Singh Nagar, Punjab, India · On-site

Semi-Conductor Laboratory (SCL); an autonomous body under Ministry of Electronics & Information Technology (MeitY), Government of India; is engaged in Research & Development in the area of Microelectronics to meet the strategic needs of the country.
Analysis and Design of CMOS Bandgap Voltage Reference using IEEE standards. Analysed various CMOS circuits. Had an exposure to clean rooms,assembly and packaging area,VLSI and Enviromental testing Labs.

CMOS