Saurabh Bhattacharya

Engineering Manager

Bengaluru, Karnataka, India13 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in managing complex semiconductor design projects.
  • Proficient in multiple physical design tools and methodologies.
  • Demonstrated leadership in team management and project execution.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and VLSI methodologies.

Contact

LinkedIn

Skills

Other Skills

Physical DesignVLSIStatic Timing AnalysisVerilogCMOSPerlTimingVHDLEncounterEDALVSTCLCalibreRTL designCadence Virtuoso

About

Experienced Physical Design Engineer with a demonstrated history of working in the semiconductor industry. Skilled in handling multiple blocks and managing a team for the execution of Projects.

Experience

13 yrs 6 mos
Total Experience
2 yrs 2 mos
Average Tenure
5 yrs 6 mos
Current Experience

Intel corporation

2 roles

Physical Design Engineering Manager

Promoted

Feb 2023 – Present · 3 yrs 3 mos · Hybrid

SOC Design Engineer

Oct 2020 – Jan 2023 · 2 yrs 3 mos · Hybrid

Tessolve semiconductor pvt. ltd.

Senior Design Engineer 2

Jul 2018 – Sep 2020 · 2 yrs 2 mos · India

Synopsys inc

AMS Layout Design Engineer II

May 2016 – Jul 2018 · 2 yrs 2 mos · Noida Area, India

  • Having experience in Memory Layouts on nodes such as 10nm and 22nm on Intel foundry.

Sankalp semiconductor pvt ltd

Senior Design Engineer

Dec 2015 – May 2016 · 5 mos · Noida

  • worked here as a consultant to ARM in Memory Layout. Have experience on nodes such as 14nm and 28nm on Foundaries namely Samsung , GF, SMIC, UMC.

Interra systems

3 roles

Senior Design Engineer

Promoted

Jul 2015 – Nov 2015 · 4 mos · Bangalore

Design Engineer

Jul 2013 – Jun 2015 · 1 yr 11 mos · Bangalore

Physical Design Trainee

Aug 2012 – Jun 2013 · 10 mos · Bangalore

  • Responsible for performing the overall backend flow from Floorplanning to Routing (PnR) of a design along with STA while clearing all possible violation which may be DRC, DRV and timing as well.

Arm

Senior Consultant

Jan 2014 – May 2016 · 2 yrs 4 mos · Noida Area, India

Education

CDAC

PG Diploma — VLSI Design

Jan 2011 – Jan 2011

Rajasthan Technical University

BTech — Electronics & Communication

Jan 2006 – Jan 2010

Modern Vidya Niketan

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