Pavan Patel — Software Engineer

—> Have gained experience over the time on large complex Block(such as SerDes, DDR)as well small SoC. —>Still gaining expertise towards clock tweaking of High speed IP to balance out the timing with respect to main clock. Floorplan challenges of high speed IP with respect to new package(InFO) Worked on various technology node from 180nm till 5nm. Tool set: Fusion, Innovus, PT, ICV, calibre, Star. —> Can debug issue in formality to reach out to root cause. -> Good understanding of CMOS and logic design. -> Well versed with verilog-HDL to write synthesizable code and self checking Test-benches. -> familiar with Tcl and PERL scripting. -> Good knowledge on STA concept. -> Good knowledge on formal verification(LEC check) —> concept driven problem solving approach. Basic knowledge on functional safety standard ISO26262 with respect to Custom SoC

Stackforce AI infers this person is a VLSI design engineer with expertise in physical design and verification.

Experience: 12 yrs 3 mos