Dayanandam Putta — Software Engineer

Results-driven VLSI professional with 14+ years of hands-on experience in the Design for Test (DFT) domain, specializing in architecting and implementing robust test solutions for complex SoCs and ASICs. I have contributed to 10+ successful tapeouts across multiple technology nodes and product segments, consistently delivering high-quality designs. My core competencies include scan insertion, ATPG, boundary scan, JTAG, and post-silicon validation, with a strong focus on improving test coverage, reducing DPPM, and optimizing test time and cost. I have a deep understanding of industry-standard tools and flows, and a proven ability to collaborate across cross-functional teams to ensure first-pass silicon #DesignForTest #DFT #ASICDesign #SoCDesign #Semiconductors #ChipDesign #ATPG #LowPowerDesign #PostSiliconDebug #JTAG #Tapeout #EDA #SiliconSuccess

Stackforce AI infers this person is a VLSI and DFT specialist in the semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 9 mos