Sachidanand Varadarajan

CEO

San Diego, California, United States33 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Accomplished engineering leader in semiconductor product development.
  • Delivered over 100 semiconductor products successfully.
  • Expertise in CPU and SoC design with strong leadership skills.
Stackforce AI infers this person is a semiconductor engineering leader with extensive experience in SoC and CPU design.

Contact

LinkedIn

Skills

Core Skills

System On A Chip (soc)Strategic LeadershipElectronic Design Automation

Other Skills

ARMASICASIC DesignAnalogCC++CMOSCPU DesignCircuitsCustom Circuit DesignDebuggingDevice DriversElectronicsEmbedded SoftwareEmbedded Systems

About

An accomplished engineering leader with end to end semiconductor product development. I have extensive experience in CPU, SoC design, Design Automation (EDA), full custom circuit design, Post-Si Engineering and extensive HW-SW co-design. Excellent leadership and problem solving skills. Delivered > 100 semiconductor products Specialties: CPU design, SoC design, Electronic Design Automation (EDA), Post-Si engineering, HW-SW co design

Experience

Qualcomm

4 roles

Vice President of Engineering

Jun 2016 – Present · 9 yrs 9 mos

  • Responsible for SoC engineering, Architecture and CPU teams
System on a Chip (SoC)Post SiliconStrategic LeadershipPhysical Design

Vice President, Engineering

Promoted

Jun 2016 – Aug 2019 · 3 yrs 2 mos

  • Qualcomm India HW lead - responsible for all SoCs and IP Cores out of India Design Center spanning multiple sites. Responsible for technical and mgmt growth
System on a Chip (SoC)Post SiliconStrategic LeadershipElectronic Design automationSoCPhysical Design

Senior Director of Engineering

Promoted

Nov 2012 – Jun 2016 · 3 yrs 7 mos

  • SOC Design
System on a Chip (SoC)Post SiliconStrategic LeadershipElectronic Design automationSoCPhysical Design

Director of Engg

Jan 2008 – Jun 2016 · 8 yrs 5 mos

  • SOC Design
System on a Chip (SoC)Post SiliconElectronic Design automationSoCPhysical Design

Intel

Engineering Manager

Jul 1997 – Jan 2008 · 10 yrs 6 mos

  • CPU Design
System on a Chip (SoC)Electronic Design automationSoCPhysical Design

Synopsys inc

R & D Engineer

Mar 1995 – Jul 1997 · 2 yrs 4 mos

  • STA tools
Electronic Design automationPhysical Design

Microchip

CAD Engineer

Jun 1994 – Mar 1995 · 9 mos

  • Layout Tools
Electronic Design automationPhysical Design

Texas instruments

Software Design Engineer

Aug 1990 – Jul 1992 · 1 yr 11 mos

  • Develop CAD tools
Electronic Design automationPhysical Design

Education

University of Louisiana at Lafayette

MS — Computer Engg

Aug 1992 – Jan 1994

Indian Institute of Science (IISc)

ME — ECE

Jan 1986 – Jan 1990

Sri Sathya Sai Institute of Higher Learning

BSc — Physics

Jan 1983 – Jan 1986

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