Sujal Jain

Product Engineer

Delhi, India9 mos experience

Key Highlights

Expert in VLSI design with hands-on experience in 7nm and 22nm technologies.
Proficient in industry-standard EDA tools and programming languages.
Strong background in physical design and verification processes.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and EDA tools.

Contact

Skills

Core Skills

Physical DesignVerification

Other Skills

Synopsys Custom CompilerCadence VirtuosoSynopsys toolsTCL programmingXilinx VivadoLTSpiceSilvaco TCADField-Programmable Gate Arrays (FPGA)PerlStatic Timing AnalysisC++Python (Programming Language)C (Programming Language)Data StructuresPrinted Circuit Board (PCB) Design

About

Innovative and detail-oriented VLSI postgraduate from IIT Patna, working with the latest technology nodes, including 7nm and 22nm at Intel Corporation. Experienced with industry-standard EDA tools including Synopsys Custom Compiler, Cadence Virtuoso, Xilinx Vivado, and LTspice. Proficient in Verilog, System Verilog, Python, C/C++, and TCL, with a strong grasp of analog and digital circuit design. Actively seeking roles in physical design, verification, STA, layout, and analog design.

Experience

9 mos

Total Experience

9 mos

Average Tenure

9 mos

Current Experience

Cadence

Product Validation Engineer II

Aug 2025 – Present · 9 mos · Noida · Hybrid

Synopsys Custom CompilerCadence VirtuosoPhysical DesignVerification

Intel corporation

PDK

Jun 2024 – Jun 2025 · 1 yr · Bengaluru · Hybrid

I am doing an internship with the Placement and Router Team of PDK Development. I gained hands-on experience with the Synopsys Custom Compiler, focusing on validating custom router PDK collaterals. My key responsibilities included creating layouts, developing pin test cases, performing various routing techniques, and conducting physical verification checks. I contributed to the validation of PDK kits such as pdk224_r1.1.2 (22nm) and pdk769_r0.9 (7nm), and worked on a live project with pdk768_r0.1 (7nm). I’m working on ICV tool. Additionally, I developed TCL automation scripts to validate power routing feature in synopsys custom compiler.

Synopsys toolsCadence VirtuosoPhysical DesignVerification