TAHER NASIRABADWALA

Product Engineer

Hyderabad, Telangana, India3 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in VLSI Domain and RTL Designing
Proficient in UVM Verification and SystemVerilog
Strong experience in IP and SoC-level verification

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in VLSI and UVM methodologies.

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Skills

Core Skills

Universal Verification Methodology (uvm)System VerilogSystemverilog

Other Skills

ShellPerlQuestasimVivadoDVECadance SimVisionDebuggingScenario TestingOperating SystemsShell ScriptingVerificationC++Python (Programming Language)Validation (Drug Manufacture)Process Qualification

About

Expertise in: - VLSI Domain, RTL Designing, SV, SVA, UVM Verification. Languages are known: - C, C++, OOPs, Core JAVA did by CCIT Amravati. Familiar with Tools: - VS code, NodRed, eclipse, DevC++. Workshop: - IoT & NodRed tools conducted by “CopperCloud IOTech Pvt. Ltd.”, Pune. Workshop Covers: - Connecting devices like fan motor to cloud using NodMcu chip and MQTT software.

Experience

3 yrs 11 mos

Total Experience

2 yrs 6 mos

Average Tenure

2 yrs 3 mos

Current Experience

Qualcomm

Design Verification Engineer

Jan 2024 – Present · 2 yrs 4 mos · Hyderabad, Telangana, India · On-site

Universal Verification Methodology (UVM)system verilog

Amd

Design Verification Engineer

Nov 2022 – Jan 2024 · 1 yr 2 mos · Hyderabad, Telangana, India · On-site

Successfully accrued 1.5 years of experience in Design Validation and Verification, primarily focusing on the Telluride VCU2 domain.
Developed and validated various designs, including Keystone B SE8 and SE9, on the Tenzing board using Vivado tools.
Proficient in Vivado tools for design development and validation.
Demonstrated expertise in working with the AXI4 protocol, encompassing the understanding of transactions on NSU, NMU master, and slave sides to configure VCU (Video Codec Unit) registers and DDR memory.
Contributed to enhancing the verification environment by creating monitor blocks to capture SSC transitions and AXI transactions.
Played a pivotal role in editing the test plan to cover all corner case scenarios and effectively addressed failures to meet customer requirements.
Acquired in-depth knowledge of Video Encoder and Decoder blocks, enabling proficient troubleshooting and issue resolution on the silicon board to meet specified requirements.
Programming languages:- Verilog, System Verilog.
● Verification Methodology:- UVM
● Protocol Knowledge:- AXI4, AHB, APB, QSPI
● Scripting languages:- Shell, PERL.
● Tools/Simulation software:- Questasim,Vivado,DVE,Cadance SimVision.
● Operating Systems:- Linux, Windows

Universal Verification Methodology (UVM)SystemVerilogShellPerlQuestasimVivado+2

Bitsilica semiconductor

Design Verification Engineer

Jun 2022 – Present · 3 yrs 11 mos · Hyderabad, Telangana, India

● Worked on IP and SoC-level verification projects for leading semiconductor clients including AMD and Qualcomm, contributing to multiple successful tape-outs.
● Developed and enhanced UVM-based verification environments, including reusable testbench components such as drivers, monitors, and scoreboards.
● Drove functional and code coverage closure across multiple IPs and SoC subsystems, achieving 100% coverage targets and ensuring robust design validation.
● Created and optimized automation scripts (Shell, Perl) to streamline regression execution, log parsing, and report generation, improving verification efficiency.
● Authored, directed and constrained-random testcases to validate complex scenarios and uncover design corner cases.
● Collaborated with design and architecture teams to review specifications, debug issues, and validate design fixes at both block and system levels.
● Demonstrated strong ownership in managing multiple IPs in parallel, ensuring timely delivery and high-quality verification outcomes.

Universal Verification Methodology (UVM)SystemVerilogShellPerl