May 2020 – Mar 2025 · 4 yrs 10 mos

• RF Digital Verification

Nov 2015 – May 2020 · 4 yrs 6 mos · Bangalore India

• Owning Verification of one of the complex IP of the chip. Verification methodology eRM
• SOC Verification using uVM, System Verilog, C
• Developed verification envs and VIPs from scratch using SV uVM for Inter Chip Buses
• Owner of the Crossbar generation for the Chip
• Crossbar simulations for fine tuning of parameters in vendor auto generated ENVs
• Performance analysis of the Blocks
• Involved in ECO implementation
• GLS Simulations
• System Scenario verification
• Post Silicon Verification of few blocks
• SOC Verification lead of the modem chip
• PHY IP Verification lead
• Leading the team of 15 engineers including SOC and IP Verification
• Exposure to Emulation
• Power Replay Simulation for Power Estimations

Mar 2015 – Oct 2015 · 7 mos · Bangalore India

• Joined Lantiq as IP Verification Engineer
• Lantiq became part of Intel

Mar 2010 – Mar 2015 · 5 yrs

• Verification Lead for the SOC for Consumer Electronics
• Transaction Layer Verification of PCIe
• USB PHY Verification

Mar 2007 – Feb 2010 · 2 yrs 11 mos

• USB IP Verification using eRM
• SOC Verification for the Consumer Electronics
• Gate Level Simulations
• USB2.0 HUB Verification
• Lead of USB 2.0 VIP Development using specman eRM

Mar 2005 – Feb 2007 · 1 yr 11 mos

• Verification of the Digital Part of the Mixed Signal Asics using Conventional Test-Benches.
• Developed the Tet Benches from Scratch
• Have worked on 3 Tape-Outs,
• Exposure to the complete execution flow of the ASIC Verification including gate level simulations