Narendra Varma Alluri

Product Engineer

Hyderabad, Telangana, India14 yrs 9 mos experience
Highly Stable

Key Highlights

  • 14+ years of experience in semiconductor frontend life-cycle.
  • Expertise in low-power and high-performance IC design.
  • Proficient in DFT automation and formal verification.
Stackforce AI infers this person is a semiconductor engineering expert with a focus on design and testing methodologies.

Contact

LinkedIn

Skills

Core Skills

Test PlanningProductization

Other Skills

Industry standardsBoundary ScanAutomatic Test EquipmentCoverage AnalysisScan InsertionBISTDFXRTL to GDSIIASICSoCSystemVerilogFunctional VerificationVerilogVLSIAMBA AHB

About

Accomplished Technical and Management professional with wide range of experience in all aspects of semiconductor frontend life-cycle from Product Architecture definition to Silicon Testing. 14+ Experience of IC engineering, hands-on experience in Design , DFT , Synth & STA for low-power and high performance designs : 55nm - 2nm Specialties: - IP Design & STA - JTAG , MBIST, BSCAN, In-system Test - Regular Scan & Scan Compression - At-Speed Transition and Stuck-ATPG - Formal Verification (Cadence Conformal) - Simulations (Cadence NC-Verilog and Synopsys VCS) - ATE Pattern bring-up - DFT Automation

Experience

14 yrs 9 mos
Total Experience
2 yrs
Average Tenure
9 mos
Current Experience

Cadence design systems (india) pvt. ltd.

Sr. Principal design engineer

Aug 2025 – Present · 9 mos · Hyderabad, Telangana, India · On-site

Amd

Senior Member of Technical Staff

Apr 2021 – Aug 2025 · 4 yrs 4 mos · Hyderabad, Telangana, India · On-site

Test PlanningIndustry standardsBoundary ScanProductization

Invecas

Member Of Technical Staff

Apr 2017 – Apr 2021 · 4 yrs · Hyderabad, Telangana, India

Test PlanningAutomatic Test EquipmentIndustry standardsBoundary ScanProductizationCoverage Analysis

Soctronics

2 roles

Sr Engineer

Promoted

Jul 2014 – Mar 2017 · 2 yrs 8 mos

  • DFT
  • Timing Analysis
  • Synthesis
  • STA
  • LEC

DFT engineer

Nov 2013 – Jul 2014 · 8 mos

  • DFT implementation , ATPG at tile level and SOC level along with pattern simulations.

Amd hyderabad

DFT engineer and Consultant

Feb 2013 – Dec 2013 · 10 mos · Hyderabad Area, India

  • Automatic Test pattern Generation - SOC level ATPG - Pattern simulation and Debug

Soctronics

2 roles

ASIC engineer

Sep 2012 – Jan 2013 · 4 mos · Hyderabad Area, India

  • IP level functional Verification of PCI express (Endpoint) using Specman E language , including other bus protocols such as AXI and AHB.

Asic Engineer

May 2011 – Nov 2011 · 6 mos · Banjara Hills, Hyderabad

  • IP level Design/verification of MIPI receiver controller including bus protocols such as AHB, APB etc and Open Verificaiton Methodology (OVM).

Amd hyderabad

ASIC Engineer and Consultant

Nov 2011 – Aug 2012 · 9 mos · Hyderabad Area, India

  • Worked on Power Management verification at SOC level.

Education

Padmasri Dr B.V Raju Institute of technology

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2007 – Jan 2011

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