Raghavendra D.

Software Engineer

Bengaluru, Karnataka, India10 yrs 2 mos experience
Highly Stable

Key Highlights

  • Experienced in Physical Design and VLSI methodologies.
  • Proficient in ASIC and SoC design processes.
  • Strong background in using Cadence and Synopsys tools.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC and SoC development.

Contact

LinkedIn

Skills

Core Skills

Physical DesignVlsi

Other Skills

DFTFloor PlansCVerilogTCLVLSI CADClock Tree SynthesisRoutingASICSoCStatic Timing AnalysisPlace & RouteScan InsertionWindowsApplication-Specific Integrated Circuits (ASIC)

Experience

10 yrs 2 mos
Total Experience
2 yrs 9 mos
Average Tenure
1 yr 10 mos
Current Experience

Amd

MTS Silicon Design Engineer

Jul 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India · Hybrid

Physical DesignDFTFloor PlansVLSICVerilog+17

Intel corporation

CPU Physical Design Engineer

Dec 2018 – Jun 2024 · 5 yrs 6 mos · Bengaluru, Karnataka, India · Hybrid

Cientra

Physical Design Engineer - II

Jun 2016 – Nov 2018 · 2 yrs 5 mos · Bengaluru, Karnataka, India

Institute of silicon systems pvt. ltd.

Physical Design Engineer

Nov 2014 – Apr 2015 · 5 mos · Greater Hyderabad Area

Education

BITS Pilani Work Integrated Learning Programmes

Master of Technology - MTech — MicroElectronics

Jul 2018 – Nov 2020

MLR Institute of Technology

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2010 – Jan 2014

Spring's High School

SSC

Jan 2002 – Jan 2008

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