Sujit Kondaveeti

Software Engineer

Hyderabad, Telangana, India16 yrs 6 mos experience
Highly Stable

Key Highlights

  • Experienced in VLSI and ASIC design.
  • Proficient in RTL coding and static timing analysis.
  • Strong background in semiconductor technologies.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and ASIC technologies.

Contact

LinkedIn

Skills

Core Skills

VlsiAsicSoc IntegrationRtl

Other Skills

DebuggingMicroprocessorsRTL codingVerilogComputer ArchitectureSystemVerilogSoCRTL designVHDLModelSimFPGASemiconductorsCadence VirtuosoStatic timing analysis

About

Experienced physical design engineer

Experience

16 yrs 6 mos
Total Experience
4 yrs 10 mos
Average Tenure
2 yrs
Current Experience

Microsoft

Physical Design Engineer

May 2024 – Present · 2 yrs · Hyderabad, Telangana, India

DebuggingMicroprocessorsRTL codingVerilogVLSIASIC+9

Apple

Physical Design Engineer

Jan 2020 – May 2024 · 4 yrs 4 mos · Portland, Oregon Area

Intel corporation

Component Design Engineer

Oct 2011 – Jan 2020 · 8 yrs 3 mos · Portland, Oregon Area

  • Experienced design engineer with 7 years of experience in circuit design, static timing analysis, SOC integration and RTL. Currently responsible for timing convergence of high speed memory subsystems on Intel's next generation SOCs.
Static timing analysisSOC integrationRTL

Portland state university

Student (Undergraduate/Graduate)

Sep 2009 – Aug 2011 · 1 yr 11 mos

  • Studied Electrical and Computer Engineering with main emphasis on VLSI.

Education

Portland State University

Masters of Engineering — Electrical and Computer engineering

Jan 2009 – Jan 2011

CVR College of engineering

Bachelors of Technology — Electronics and Communication Engineering

Jan 2005 – Jan 2009

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