Nov 2022 – Apr 2025 · 2 yrs 5 mos · Bengaluru, Karnataka, India

• Amazon devices (LAB126) working on low power SoCs for Alexa echo, fireTV, firestick, kindle, tablets etc.
• Front End: Synthesis, Timing constraints generation, Low power UPF.
• Backend: Physical Design, methodologies
• Signoff: STA, FV/CLP, Power etc.

Jan 2021 – Nov 2022 · 1 yr 10 mos · On-site

• 3nm PNR & STA, Flow Methodology
• 3DIC Implementation

Aug 2018 – Dec 2020 · 2 yrs 4 mos · On-site

• Designing ASICs on unprecedented technology nodes. Block level closure: Physical design, Static Timing Analysis and PV to achieve early analysis and silicon maturity.
• Timing libs analysis across corners to get an idea about new PDKs which helps PnR to PT correlations and corner mapping.
• Also, involved in SoC Integration: IP placement, RDL Routing , Bump Placement, IO Pads and ESD placements and other full chip activities.
• Tech Nodes:
• 4nm, 5nm, 7nm
• Tools: Fusion Compiler, Innovus, starRC, PrimeTime, conformal, Calibre etc.

Jun 2015 – Aug 2018 · 3 yrs 2 mos · Ahmedabad Area, India

• Project 3: Working on 16nm FF+ technology, Handling 5 Blocks for complete PnR and Signoff cycle. Block size: > 1.5X2mm, >2M instance count
• Clocks: 2 functional clocks, 1.6Ghz, 1Ghz
• Working closely with designers and SoC team for better convergence.
• Tools: Synopsys suit (ICC2, PT, StarRC), calibre, conformal
• Project 2: Working on 16nm FF+ technology, Handling multiple blocks for complete synthesis, PnR and signoff (RTL to GDS) Blocks include digital (1Ghz) and custom(IOPADs). Debugging flow.
• Floorplan, STA, placement, CTS, routing, signoff, timing closure, LVS, DRC clean up, LEC, Power analysis (EM/IR).
• Tools:
• Lynx design system: Automation
• IC Compiler: PnR
• Compiler DC: Synthesis
• ICV/calibre: Physical Verification
• Conformal : LEC
• Project 1: Worked as a script developer for a automation tool and gui system as a part of project and initiative from eInfochips. Major work was to develop important TCL scripts and to integrate them with the tool. Also had a change to hands on TCL/TK platform.

Jan 2015 – Jun 2015 · 5 mos · Ahmedabad , India

• 1) Project: Complete PD flow on a block having 41K cells, 32 memories, 1.1GHz, 16nm FinFet using Cadence Encounter.
• 2) Projects and training on physical design aspects of chip designing: synopsys ICC.
• Floorplanning
• Placement
• CTS/CTO
• Route
• Physical verification: LEC, LVS, rule checks: DRC, ERC, Antenna checks ARC, IR drop, EM, Via checks
• STA with PT
• Synthesis, simulation: verilog RTL and testbenches.
• Scripting: TCL, Perl, shell
• Platforms: linux: Radhat, centos, ubuntu.

Mar 2014 – Jan 2015 · 10 mos · Morristown, NJ

• Recruiting for semiconductor clients.
• Short listing resumes, salary negotiation, Visa advise, Project co-ordination.