Dharmendra Kumar — Software Engineer
SOC Design Engineer • Proven experience in leading and managing RTL design teams, taking ownership of IP development and netlist-level handoff to SoC integration. • Skilled in microarchitecture definition and RTL coding using Verilog/SystemVerilog. • Extensive hands-on experience in RTL quality checks and debug using tools like Spyglass Lint, CDC, and RDC, ensuring clean design sign-off. • Proficient in implementing SDC constraints, logic synthesis , LEC, and timing closure. • In-depth knowledge of clock and reset architectures, and designing for low-power, multi-clock domain Designs. Experience in functional ECOs at the netlist level using industry tools and scripting for efficient change implementation ASIC Tools • Proficient in Synopsys and Cadence tool suits • VCS,CDC/RDC,DC/FC, LEC, PT
Stackforce AI infers this person is a semiconductor design engineer with expertise in RTL and SoC development.
Location: Bengaluru, Karnataka, India
Experience: 12 yrs 11 mos
Skills
- Rtl Design
- Microarchitecture
- Logic Synthesis
- Static Timing Analysis
Career Highlights
- Expert in RTL design and SoC integration.
- Proficient in low-power and multi-clock domain designs.
- Experienced in leading RTL design teams at Intel.
Work Experience
Intel Corporation
SOC Design Engineer (9 mos)
IP Logic Design Engineer (7 yrs)
Qualcomm
Design Engineer (6 mos)
Intel Corporation
Physical Design Engineer (2 yrs 3 mos)
Incise Infotech Private Limited
Design Engineer (5 yrs 2 mos)
Education
Bachelor's degree at Lingayas University
