Mallina Rajesh

Software Engineer

Bengaluru, Karnataka, India18 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over a decade of experience in VLSI design.
  • Expertise in SOC design implementation at AMD.
  • Proven track record in timing closure for complex processors.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in VLSI and physical design.

Contact

LinkedIn

Skills

Core Skills

VlsiPhysical DesignTiming Closure

Other Skills

Static Timing AnalysisProcessorsEDAASICSoCLogic SynthesisRTL designVerilogRTL Synthesis

Experience

18 yrs 7 mos
Total Experience
9 yrs 3 mos
Average Tenure
15 yrs 4 mos
Current Experience

Amd

Senior Design Engineer

Dec 2010 – Present · 15 yrs 4 mos

  • Currently working in the SOC Design Implementation team on Custom Designs
VLSIPhysical DesignStatic Timing AnalysisProcessorsEDATiming Closure+5

Ibm india private limited

R & D Engineer

Aug 2007 – Nov 2010 · 3 yrs 3 mos

  • Have worked for 3 years and 4 months as a Back End Physical Design Engineer on IBM RISC and CISC Processors where i handled Customs and Synthesizable designs from RTL Synthesis to Timing closure.
  • Have worked on 45nm and 32nm Techonlogies.
VLSIPhysical DesignStatic Timing AnalysisProcessorsEDATiming Closure+5

Education

Vellore Institute of Technology

M.Tech — VLSI DESIGN

Jan 2005 – Jan 2007

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