K

Kishor Shivhare

Software Engineer

Noida, Uttar Pradesh, India15 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 14+ years in Functional Verification.
  • Expert in developing scalable verification environments.
  • Strong background in protocol verification.
Stackforce AI infers this person is a seasoned expert in Hardware Design and Verification within the semiconductor industry.

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Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

VerilogPCIe

About

14+ years of experience in Functional Verification of complex sub-system and IP-level designs using SystemVerilog and UVM. Proven expertise in developing scalable, reusable verification environments, writing test cases, assertions, and achieving complete functional and code coverage. Strong background in protocol verification (PCIe, AXI, AHB, APB, OCP, IPS, USB, etc.) and hands-on experience with industry-standard tools like Synopsys VCS, Cadence NCSim, and QuestaSim. Adept at debugging, regression management, and collaborating with cross-functional teams to ensure first-pass silicon success.

Experience

15 yrs 6 mos
Total Experience
3 yrs 10 mos
Average Tenure
5 yrs 10 mos
Current Experience

Nxp semiconductors

2 roles

Principal Engineer

Promoted

Apr 2024Present · 2 yrs 1 mo · Noida, Uttar Pradesh, India

Universal Verification Methodology (UVM)SystemVerilog

Staff Engineer

Jul 2020Jun 2024 · 3 yrs 11 mos · Noida, Uttar Pradesh, India

Universal Verification Methodology (UVM)SystemVerilog

Qualcomm

2 roles

Senior Lead Engineer

Promoted

Dec 2018Jul 2020 · 1 yr 7 mos

Universal Verification Methodology (UVM)SystemVerilog

Senior Engineer

May 2016Nov 2018 · 2 yrs 6 mos

Universal Verification Methodology (UVM)SystemVerilog

Samsung r&d institute india - bangalore private limited

Senior Hardware Engineer

Feb 2013May 2016 · 3 yrs 3 mos · Noida

Universal Verification Methodology (UVM)SystemVerilog

Wipro technologies

Verification Engineer at VLSI field

Oct 2010Feb 2013 · 2 yrs 4 mos · Pune

Universal Verification Methodology (UVM)SystemVerilog

Education

Jabalpur Engineering College

Bachelor of Engineering (BEng)

Jan 2006Jan 2010

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