Dayananda Sagar

Software Engineer

Bengaluru, Karnataka, India13 yrs 1 mo experience

Highly Stable

Key Highlights

Strong expertise in VLSI and ASIC verification.
Hands-on experience with Cadence tools for circuit design.
Proven track record in analog and digital design projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with strong VLSI and ASIC verification expertise.

Contact

Skills

Core Skills

Physical DesignStandard Cell DevelopmentAnalog DesignOscillator Design

Other Skills

14nm layouts10nm layoutsStandard cell layoutsQualification flowCommunication with schematic teamRelaxation Oscillator designCMOS Ring Oscillator designCadence VirtuosoPre-layout simulationPost-layout simulationVLSIASIC verificationRTL designingCMOS VLSIlow power VLSI

About

I did my internship at National semiconductor and worked on Oscillator project for 7months. then i found there are very few opportunities in analog domain for a fresher so decided to go to verification domain for which freshers play vital role in VLSI industries hence joined Maven to gain knowledge in ASIC verification and now i am doing good in this field. my short term goal in to gain good knowledge in VLSI verification domain. and long term goal is to be a team lead in lower tier company down the 5 years. Specialties: Very strong knowledge in Digital design, good hands on experience in design combinational and sequential circuits. good understanding of ASIC and FPGA flow.

Experience

13 yrs 1 mo

Total Experience

2 yrs 7 mos

Average Tenure

Current Experience

Amd

2 roles

Member of Technical Staff Silicon design Engineer

Jul 2024 – Aug 2024 · 1 mo · Singapore

Senior silicon design engineer

Feb 2022 – Aug 2024 · 2 yrs 6 mos · Singapore

Xilinx

Design Engineer

Oct 2016 – Feb 2022 · 5 yrs 4 mos · Singapore

Intel corporation

Physical Design Engineer

Aug 2015 – Sep 2016 · 1 yr 1 mo · Bangalore

o Worked on 14nm and 10nm layouts
Was handling a team of 2 from a service company.
Understanding architecture for 14nm and 10nm technology nodes.
Responsible for creating qualification flow for standard cell layouts and other deliverables.
Was continuously communicating with schematic team for design improvement.

14nm layouts10nm layoutsStandard cell layoutsQualification flowCommunication with schematic teamPhysical Design+1

Sankalp semiconductors pvt ltd

Design Engineer

Dec 2011 – Jul 2015 · 3 yrs 7 mos · Hubli Area, India

National semiconductor india pvt ltd

Project 1

Dec 2010 – Jul 2011 · 7 mos · Bangalore

1.5mW, 250ppmC Fully integrated 12Mhz Relaxation Oscillator for capacitor
sensor application. (With Layout)
Project 2 : 800W, 12 MHz CMOS Ring Oscillator as Frequency reference circuit.
Tool Used : CADENCE Virtuoso Analog Design Environment.
Roles and responsibility in the project work.
Design the circuit using schematic.
Pre-layout simulation using Cadence analog design environment.
Extract the layout for the design, perform place and route verify using Assura DRC, LVS and debug.
RC extraction of the drawn layout.
Post layout simulation using Spectre and verify result. Also perform trimming for accuracy.
Engineering Academic Project work
ON E-WAITER WITH WIRELESS SERVER AND BILLING SYSTEM FOR HOTELS.
This project is designed to provide us with a simple and effective system to automate the process of "placing the order" for food & beverage items in the hotels. The project presented here does the perfect job saving time in fast food hotels and other hotels where in quick serve are more important over the leisure experience.