Abhishek Tyagi

Software Engineer

Delhi, India7 yrs 6 mos experience

Highly Stable

Key Highlights

Expert in Digital Circuit Design and Timing Closure.
Proven experience in leading semiconductor projects.
Skilled in using advanced tools like Synopsys Primetime.

Stackforce AI infers this person is a semiconductor design engineer with expertise in digital circuit design and timing analysis.

Contact

Skills

Core Skills

Static Timing AnalysisDigital Circuit Design

Other Skills

TweakerSynopsys PrimetimeLECPrimetimePtecoTCLDesign Rule Checking (DRC)Logic DesignApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)Field-Programmable Gate Arrays (FPGA)VerilogunixCPNR

About

Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Digital Circuit Design, Timing Closure, LEC.

Experience

7 yrs 6 mos

Total Experience

3 yrs 9 mos

Average Tenure

Current Experience

Qualcomm

2 roles

Senior Lead Engineer

Dec 2023 – Feb 2025 · 1 yr 2 mos · Noida, Uttar Pradesh, India · On-site

Static Timing AnalysisTweaker

Senior STA Engineer

Apr 2021 – Dec 2023 · 2 yrs 8 mos · Noida, Uttar Pradesh, India · On-site

Static Timing AnalysisSynopsys Primetime

Intel corporation

2 roles

Digital circuit Design Engineer

May 2018 – Apr 2021 · 2 yrs 11 mos

Worked on circuit designing of cpu core blocks on cutting edge technologies ( 14nm, 10nm, 7nm ).
Responsible for timing closure of the blocks along with Design rule Checks and meeting Power targets .

Static Timing AnalysisLECDigital Circuit Design