Venkat Malluri — Director of Engineering

A highly motivated and dynamic People Manager and Technical Lead with over 20+ years of experience in ASIC Physical Design. Proven silicon experience with 20+ tape outs of multimillion gates, high speed, low power and complex chips with varying process nodes from 65nm to 16nm. Extensive experience in physical design manger role as well as an individual contributor at Broadcom, AMD, ATI Technologies and Qualcore Logic limited. Very proficient in all stages of ASIC physical design both at Fullchip as well as block level which includes expertise in Floorplan, Placement, CTS, Optimization, Routing, Timing Closure, Crosstalk analysis, Electrical fixes, Eco cycles and Physical closure. Experience in leading team of engineers from Netlist to GDSII for several projects. Experience in training PD engineers on tools, flow and methodologies. Proficient in using EDA tools of cadence, synopsys and mentor graphics like SOC Encounter, Nanoroute, Celtic, Conformal, IC compiler, Star-RC extraction,PrimeTime SI, Caliber.

Stackforce AI infers this person is a seasoned ASIC Physical Design Engineer with extensive experience in semiconductor design.

Location: Hyderabad, Telangana, India

Experience: 25 yrs 6 mos