H

Hari D

Software Engineer

Bengaluru, Karnataka, India9 yrs 4 mos experience
Highly Stable

Key Highlights

  • Experienced in ASIC design and verification.
  • Proficient in Verilog and UVM methodologies.
  • Strong background in VLSI and functional verification.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and VLSI technologies.

Contact

LinkedIn

Skills

Other Skills

Verilogsystem verilogMicrosoft OfficeUniversal Verification Methodology (UVM)Functional VerificationApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)RTL Design

Experience

9 yrs 4 mos
Total Experience
8 yrs 8 mos
Average Tenure
8 mos
Current Experience

Amd

Senior Verification Engineer

Sep 2025 – Present · 8 mos

Sisoc semiconductor technologies pvt ltd.

2 roles

ASIC Verification engineer

Jun 2017 – Sep 2025 · 8 yrs 3 mos · Bangalore

ASIC Design and Verification intern

Dec 2016 – May 2017 · 5 mos · Bangalore

Education

JNTU Anantapur

Bachelor of Technology - BTech

Jun 2013 – May 2017

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