Dhyanik Pujara

CTO

Santa Clara, California, United States2 yrs 2 mos experience

Key Highlights

Expert in GPU architecture and design.
Proven experience in hardware engineering and verification.
Strong leadership in team management and project execution.

Stackforce AI infers this person is a Hardware Engineering and GPU Architecture specialist.

Contact

Skills

Core Skills

Computer ArchitectureRtl DesignComputer EngineeringHardware DesignTeam ManagementOperations ManagementEmbedded SystemsC++

Other Skills

Verilogmemory hierarchyVHDLHardware TestingHardware EngineeringElectrical EngineeringMulti-functionalRTL VerificationMarketing StrategyTechnical WritingEvent ManagementM5-StackSD Card InterfacingConsultingComputer Programming

Experience

2 yrs 2 mos

Total Experience

1 yr 11 mos

Average Tenure

3 mos

Current Experience

Nvidia

2 roles

GPU Architect

Feb 2026 – Present · 3 mos · Santa Clara, CA

Architect Intern

May 2025 – Aug 2025 · 3 mos · Santa Clara, California, United States · On-site

Integrated AI Workflows into GPU SOC Functional Modeling Platform.

University of southern california

Grader

Aug 2025 – Dec 2025 · 4 mos

EE557 Computer Systems Architecture by prof. Murali Annavaram

Usc information sciences institute

Student Researcher Intern

Jan 2025 – Mar 2025 · 2 mos · Marina del Rey, California, United States · Remote

Tracer Project, Accelerator Design and Simulation for DARPA.

VerilogComputer ArchitectureRTL Designmemory hierarchyC++

Isro - indian space research organization

Research Intern

Jan 2024 – May 2024 · 4 mos · Ahmedabad, Gujarat, India · On-site

Designed and implemented an IEEE-754 compliant Floating Point Co-Processor (FPC) considering PPA. The goal was to compute phase for each antenna belonging to a phased array SAR.
Designed an Architecture comprised of Register, SFRs, DPRAM and BUS interface, and ISA of 19 custom instructions.
Proposed and verified APB and AHB wrappers for signal conversion for data transfer through respective buses.
Devised Custom Instructions cos and sin to achieve a speedup of 33% and 38% respectively. Overall speedup of 51% was achieved to compute phase for one antenna.
Verified the DUT on Questa Sim using a VHDL testbench and hex file (generated by compiling a C code).
Achieved 100% code coverage, conducted linting, and performed RTL synthesis using Xilinx ISE

Computer EngineeringRTL DesignVHDLHardware TestingHardware EngineeringComputer Architecture+4

Eco - electronics and communication students' organisation

2 roles

President

Promoted

Jan 2023 – Dec 2023 · 11 mos

Team ManagementMarketing StrategyTechnical WritingOperations ManagementEvent ManagementMulti-functional

Executive Member

Jan 2022 – Jan 2023 · 1 yr

Ocean abrasive

Embedded Product Development Intern

Jan 2023 – May 2023 · 4 mos · Surat, Gujarat, India · Hybrid

Deployed a resilient and user-friendly Data Acquisition System using M5-Stack and ESP32 development board, resulting in a 55% reduction in wheel production time.
Improved labor efficiency by halving the required workforce from 2 to 1 per weighing machine node.

M5-StackEmbedded SystemsSD Card InterfacingConsultingC++