Chanda Gupta

Software Engineer

Hyderabad, Telangana, India7 yrs 9 mos experience

Highly Stable

Key Highlights

Led successful post-silicon validation for multiple Intel SoCs.
Achieved 80%+ success rate in resolving system-level power management issues.
Developed automation frameworks that optimized costs and improved validation coverage.

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in power management and debugging.

Contact

Skills

Core Skills

Power ManagementDebuggingAutomation

Other Skills

Windows DebuggerMIPI60-based XDPLauterbachLogic AnalyzersOscilloscopesWindbgTest PlanningMATLAB3G TechnologyTeam LeadershipTest Plan DevelopmentWindowsCommunicationOperating SystemsArchitecture

About

- Experienced Senior Debug Validation Engineer with 6+ years of experience in Intel, specializing in CPU core architecture, post-silicon validation, power management, and system-level debug on cutting-edge Intel platforms. - Proven track record of leading post silicon validation, integration, debugging, and resolving system level issues, with expertise in complex power management features and cross-functional collaboration. Skill set: - OS: Windows - Languages: C, C++, C#, Python - SoCs: Intel Big Core, Intel Atom - Debug Tools: Windows Debugger, Saleae Logic Analyzers, MIPI60-based XDP, Lauterbach, Oscilloscopes

Experience

7 yrs 9 mos

Total Experience

7 yrs 9 mos

Average Tenure

7 yrs 9 mos

Current Experience

Intel corporation

3 roles

Senior Debug Validation Enginner

Promoted

Apr 2022 – Present · 4 yrs 1 mo · On-site

Led the debugging and resolution of system-level power management issues (Hard Hangs, Machine Checks, Soft Hangs) using tools like MIPI60-based XDP, Lauterbach, Logic Analyzers, and Oscilloscopes, Windbg achieving an 80%+ success rate.
Drove Post-Silicon validation milestones for SoC Arrow Lake, Meteor Lake, and Alder Lake with successful completion.
Led platform validation and debug milestones with 50% team resources, ensuring project success and meeting tight deadlines.
Drove root-cause analysis task forces for silicon bugs, software issues, and firmware interactions.
Mentored junior engineers and contributed to the improvement of existing systems and processes by identifying deficiencies, conducting root cause analysis, and implementing solutions.
Delivered automated telemetry log analysis and test case automation within 3 months.
Created Automation Framework for Debug and Telemetry to optimize 20% cost and have full validation coverage.

Power ManagementAutomationDebuggingWindows DebuggerMIPI60-based XDPLauterbach+3

Software Engineer

Promoted

Sep 2019 – Mar 2022 · 2 yrs 6 mos · On-site

Worked as an individual contributor for enabling and debugging key platform power management flows(Modern Standby, S3, S4, S5, WR, RTD3) in Comet Lake, and Alder Lake.
Drove task forces to resolve high-impact issues across multiple technical domains(PMC, BIOS and OS).

Power ManagementTest Planning

System Engineer

Jul 2018 – Sep 2019 · 1 yr 2 mos · On-site

Analyzed receiver-side network data from Apple devices for physical SIM and eSIM to assess 3G/4G LTE performance.
Evaluated key KPIs including availability, accessibility, retainability, and throughput to support dual SIM optimization.

MATLAB3G Technology