Chaitanya Vahni Vaddadi

Director of Engineering

Bengaluru, Karnataka, India20 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 15+ years in Digital IP design and RTL architecture.
  • Expertise in High Level Synthesis and MATLAB modeling.
  • Proven track record in project management and cross-cultural collaboration.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Digital IP and Mixed Signal design.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignIp DesignDigital DesignProject ManagementHardware DesignMixed Signal DesignIntegration SupportVerificationCustomer SupportCad Support

Other Skills

MIPI subsystemSynopsys DesignwareImaging AlgorithmsMATLAB modelingNAND Flash memory controllerDRAM memory subsystemPower management IPsClock management IPsDMA controllerSTAIP DVEVC DVPower management EVCLayout creationMask alignment

About

Digital Design Engineer with 15+ years experience in Frontend design (RTL/Micro architecture) with expertise in Digital IP design. My experience also includes High Level Synthesis (HLS) design ( System C , C++), MATLAB modeling, Digital part of Mixed Signal design & IP verification.

Experience

20 yrs 11 mos
Total Experience
3 yrs
Average Tenure
3 yrs
Current Experience

Samsung semiconductor india

Associate Technical Director

Apr 2023 – Present · 3 yrs · Bengaluru, Karnataka, India · On-site

Intel corporation

2 roles

Engineering Manager

Nov 2021 – Mar 2023 · 1 yr 4 mos

Senior Design Lead

Jan 2019 – Nov 2021 · 2 yrs 10 mos

  • Executed SOC RTL design for camera facing Mobile Industry Processor Interface (MIPI) subsystem using Synopsys Designware components. Intel point of contact for other subsystems created using contractors.
RTL designMIPI subsystemSynopsys DesignwareIP design

Canon, inc.

ASIC Digital Design Engineer

Mar 2018 – Dec 2018 · 9 mos · Tokyo, Japan

  • Shifted to Canon Japan on Global assignment program to gain cross cultural exposure.
  • Developed Imaging Algorithms (BSM & C model creation)
  • Analysis of MATLAB algorithms to generate hardware implementable block diagrams and specifications.
  • Project Management: Coordinating project schedule and execution to deliver ontime with Indian counterparts.
Imaging AlgorithmsMATLAB modelingProject ManagementDigital design

Canon india

Lead Engineer

Jan 2015 – Feb 2018 · 3 yrs 1 mo · Bengaluru Area, India

  • Hardware design: Development of NAND Flash memory controller from scratch which includes MATLAB modeling and analysis of error correction coding modules.
  • Development of proof of concept architecture for DRAM memory subsystem.
  • Development of Imaging algorithms.
  • Ensured the techinal issues for all projects were resolved ontime with quality.
NAND Flash memory controllerDRAM memory subsystemImaging algorithmsHardware designProject Management

Nxp semiconductors

Tech Lead

Jan 2013 – Jan 2015 · 2 yrs · Bengaluru Area, India

  • Mixed signal design(digital part)
  • Design of power management IPs.
  • Design of Clock management IPs.
  • Arm based SOC design.
  • Worked on Hardware software co-design flow.
Mixed signal designPower management IPsClock management IPsIP design

Texas instruments

2 roles

Frontend Specialist

Promoted

May 2008 – Dec 2012 · 4 yrs 7 mos

  • IP design: Spec to timing closed RTL netlist,
  • support for SOC teams/backed teams on integration/STA/GLS issues, ECO, customer support.
  • Worked on multiple IP's. Developed DMA controller from scratch.
  • Managed subcontractors on execution of some projects.
  • Worked on Hardware software co-design flow
IP designDMA controllerSTAIntegration support

Design Engineer

Jun 2006 – May 2008 · 1 yr 11 mos

  • IP DV,evc DV: Spec to Verification closure, GLS, customer support.
  • Guided 10 different teams in efficient usage of a power management EVC.
IP DVEVC DVPower management EVCVerificationCustomer support

Cypress semiconductor

2 roles

CAD support engineer

Jul 2005 – Jun 2006 · 11 mos · Bengaluru Area, India

  • Manual , automatic layout creation for R&D analysis,
  • Final masks& Frames alignment checking.
  • Pro-actively extended the scope of my project to achieve 40 % higher layout automation.
Layout creationMask alignmentCAD support

Co-op graduate

Dec 2004 – Jun 2005 · 6 mos · Bengaluru Area, India

  • IBIS models generation, layout automation.
IBIS models generationLayout automation

Education

International Institute of Information Technology Hyderabad (IIITH)

MTech — VLSI & Embedded systems

Jan 2003 – Jan 2005

Indian Institute of Management, Calcutta

Executive Program in Global Bussiness Management

Jan 2015 – Jan 2016

Muffakham Jah College of Engineering & Technology

BE — Electronics and communication

Jan 1999 – Jan 2003

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