Jan 2013 – Sep 2014 · 1 yr 8 mos · Bangalore

• Key areas of work :
• o. GPU fullchip test running, triaging and debug
• skills : GPU verification setup understanding and debug skills
• o. GPU compute test writing (C++), trace generation and C model debug
• skills : C++, GPU compute setup understanding and debug
• o. Verifying unit level clock gating mechanism through RTL-RTL equivalence checking
• skills : Formal tools (equivalence checking), Verilog
• o. Verifying unit level context switching mechanism through RTL-RTL equivalence checking
• skills : Formal tools (equivalence checking), Verilog

Mar 2010 – Dec 2012 · 2 yrs 9 mos · Bangalore

• Key areas of work :
• Design for Debug (DFD)
• o. Verified boundary scan architecture for multiple chips (using JTV tool)
• skills : JTAG, Boundary SCan, JTV tool
• o. Verified PCIE loopback mechanism (DFD feature)
• skills : C++, JTAG
• o. Verified Cache Resident Self Test (DFD feature)
• skills : C++, SystemVerilog, JTAG

Dec 2007 – Mar 2010 · 2 yrs 3 mos

• Work experience at NXP:
• 1. SystemC model development for Audio IP's
• 2. SystemC model development for DMA
• 3. 80C51MX CPU modeling in SystemC
• 4. Memory Management Unit model for 80C51MX CPU
• 5. Test case debug using disassembled instruction trace
• 6. System Integration and validation of NFC SoC
• 7. Benchmarking of SystemC models against RTL for timing accuracy
• 8. Performance optimization of SystemC models and SoC
• 9. Cycle accuracy measurement and tuning of SystemC IP's
• 10. Keil integration of the Virtual Prototype for enabling software development

Jul 2006 – Dec 2007 · 1 yr 5 mos

• Responsible for:
• 1. Understanding SoC clocking, reset and power management schemes
• 2. Writing verification plan for ASIC block
• 3. Specman testbench development for SoC clocking module
• 4. Test case creation in e, debugging in specman and coverage analysis
• 5. Writing System Level HW/SW cosimulation test cases in C and RTL debugging
• 6. IP integration in subsystem level
• 7. RTL debug using Debussy
• 8. Test case documentation and tracking
• 9. Regression Automation
• 10. Gate level simulation for selected test cases

Jul 2005 – Dec 2007 · 2 yrs 5 mos

• 1. SystemC model development for DMA
• 2. algorithm development for tier-II coding of JPEG 2000 IP.
• 3. RTL debug of processor design and coverage analysis