Hardik Saxena

Software Engineer

Udaipur, Rajasthan, India4 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in timing analysis and hardware design.
  • Strong collaboration skills between analog and digital teams.
  • Proficient in Caliber violations and static timing analysis.
Stackforce AI infers this person is a Hardware Design Engineer with expertise in timing analysis and design engineering.

Contact

Skills

Core Skills

Timing AnalysisHardware DesignDesign EngineeringChip DesignStatic Timing AnalysisCaliber Violations

Other Skills

Timing and routing convergence signoffETM based deliveryCaliber violations checkSmart flops insertionRepeater insertionCode coverage reductionCollaboration with analog and digital teamsChip level design checksCaliber rules understandingViolation analysisTiming report analysisProtection schemesFault analysisPerlSynopsys Primetime

Experience

4 yrs 10 mos
Total Experience
2 yrs 5 mos
Average Tenure
4 yrs 1 mo
Current Experience

Intel corporation

Graphics Hardware Design Engineer

Apr 2022Present · 4 yrs 1 mo

  • Timing and routing convergence signoff at FC level
  • ETM based delivery to other IPs
  • Caliber violations check and resolution
  • Smart flops and repeater insertion at FC level
Timing and routing convergence signoffETM based deliveryCaliber violations checkSmart flops insertionRepeater insertionTiming Analysis+1

Silicon labs

Design Engineer

Jul 2021Apr 2022 · 9 mos · India

  • Reduction of different types of code coverages
  • Mediates and works with both analog (RF) team and design (digital) team
  • Responsible for chip level design checks with various tools
Code coverage reductionCollaboration with analog and digital teamsChip level design checksDesign EngineeringChip Design

Intel corporation

Full-chip Timing Analysis and Caliber Violations

Aug 2020Dec 2020 · 4 mos · India

  • Understanding the Caliber rules and different violations associated with it
  • Analysis of violations on multiple sections/partitions simultaneously
  • Analyzing timing reports generated in PrimeTime
  • Basic knowledge about static timing analysis
Caliber rules understandingViolation analysisTiming report analysisStatic Timing AnalysisCaliber Violations

Powergrid corporation of india ltd

Protection Schemes used in a substation

May 2019Jul 2019 · 2 mos · India

  • The project mainly focused on three major components of a substation, viz., transformers, transmission lines, and bus-bars.
  • Learned about the different types of faults resulting in these types of equipment and the protection schemes to prevent them.
Protection schemesFault analysis

Education

Birla Institute of Technology and Science, Pilani

Bachelor of Engineering - BE — Electrical and Electronics Engineering

Jan 2017Jan 2021

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