Vinayalingam L — CTO

As an engineering head, having Overall 16 years experience in Semicon field from RTL to GDS2 technically in low power chip designs with optimization techniques at Tosiba's chip architecture.At the forefront of semiconductor innovation, engineering leadership and a deep understanding of physical design and verification domain with STA timing challenges. Our team's mission revolves around pushing the boundaries of technology and optimizing design processes with team buildinh. Hiring talented strong technical folks for the service on full chip multi voltage domain,low power designs.Worked from 45nm CMOS to 4nm FINFET lower nm latest projects with block, sub system , full chip implementation.Exploring on 3nm/2nm test chips. Accomplished Samsung, GF, IFS and TSMC foundries flow with DTV,CPU,GPU,PLL, Mobile, memory, Graphics, ARM Cortex complex processor chips with complex high speed LPDDR, PCIe IPs as well with low power designs to Achieve better TAT as well.Exposed with Makeflow, AMD FCT- Tile builder flow, Cheetah2, NB flow designs for the fab based projects for different customers complex designs.As a Project Lead at Intel Corporation through TechM, I honed expertise in technical recruiting and TCL scripting, handled tech leads technically from scratch to end of the project.GTCHE CAD flow development, contributing to substantial project advancements from RTL to GDSll within the given time limit to achieve better PPA. Together with a talented team, we championed initiatives that bolstered efficiency and product excellence with fast pace turn around time and EMIR mitigation with much tape outs of the design successfully.Collaborated closely with cross-functional teams including Design, verification, packaging teams to ensure smooth and efficient project execution along with stakeholder management.Validating and delivering projects to a fabrication. worked closely with post silicon validation team before releasing to market.Exploring with upcoming 3DIC, AI, quantum chips, Intel's 1.8nm Backend metal design with TPU, NPU .. implementations.Hired couple of hundred good talented candidates across PD, PV, EMIR and full chip experts with block owners.Worked with DTV, mobile, memory,networking test chip, ARM cortex processor based complex chips.Pursuing 2nd year global DBA Research in Emerging technologies at Switzerland's Rushford business school. Parallelly working on publishing papers to international conferences by numerous literature survey and research on confidential global business impacts of AI insights on Semiconductor domain.

Stackforce AI infers this person is a semiconductor engineering leader with a focus on low power design and project management.

Location: Bengaluru, Karnataka, India

Experience: 15 yrs 5 mos