Koti Reddy

Software Engineer

Bengaluru, Karnataka, India12 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC design and physical verification.
Proficient in automation scripting for DRC fixes.
Experience with advanced technology nodes like 10nm.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in ASIC design and verification.

Contact

Skills

Core Skills

AsicPhysical Design

Other Skills

ASIC flow and APR flowsStatic Timing AnalysisCMOSDigital ElectronicsASIC flowFloor planningPower planningPlacementCTSRoutingPhysical verificationDRCtcl scriptingAutomation scriptsIC Compiler

About

An enthusiastic and self-motivated experienced Physical design engineer looking for a challenging and responsible position as Physical design engineer to apply my knowledge and skill with my hard work and patience,and be world class in ASIC design.

Experience

12 yrs 8 mos

Total Experience

2 yrs 6 mos

Average Tenure

3 yrs 8 mos

Current Experience

Amd

Senior Silicon Design Engineer

Sep 2022 – Present · 3 yrs 8 mos · Bengaluru, Karnataka, India

ASIC flow and APR flowsStatic Timing AnalysisCMOSDigital ElectronicsASICPhysical Design

Intel corporation

2 roles

SOC Design Engineer

Nov 2020 – Sep 2022 · 1 yr 10 mos

Physical Design & Verification Engineer

Oct 2017 – Nov 2020 · 3 yrs 1 mo

Knowledge on ASIC flow (RTL to Oasis/GDSII) & APR flow.
 Good Background on Physical Design : Floor planning, Power planning( IR Drop Analysis),
Placement, CTS and Routing.
 Worked on physical verification (Signoff1p0).
 Worked on most of the DRC’s & trclvs (Tool used: Synopsys IC Compiler/Validator).
 Worked on solving Latch up, EM, IR Drop, Antenna effect, Crosstalk and DFM.
 Implementing ECO’s: upsizing/downsizing, buffer insertion, net improvement, shielding to fix signal integrity and timing fixes etc.
 Worked on Health Checks related DRC’s.
 Written Automation scripts to fix DRC’s (tcl scripting).
 Worked on 10+++ (Wave3), 10 nm and 14 nm technology nodes.
 Working on Analog and top metal routes for 10nm SoC chip
 Optimized Analog routes based on IR/R analysis report to meet the specifications from power delivery team.
 Have exposure to industry standard tools like IC Compiler, IC Complier II, ICV and Redhawk.

ASIC flowPhysical DesignFloor planningPower planningPlacementCTS+6

Rv-vlsi vlsi and embedded systems design center

Physical Design Trainee

Mar 2017 – Sep 2017 · 6 mos · banglore

Block Level Implementation Of Lakshya Sub System
Description :
Block level implementation of lakshya sub system.Scaling technology : 40nm, Macro count -
34, Standard cell count-38887,Area - 4.2 mm2,Supply Voltage : 1.1,power budget : 600mW ,IR
drop < 55mV, Metal Layers : 7.
Tools :
IC Complier from synopsys
Challenges :
Floorplanning - The main challenge of this project was to design floorplan. The floorplan
should be such that it doesn't violates the IR drop requirement.
Power Planning- During the power planning the main challenge was to get the tracks placed
properly without any overlaps, missing tracks. The pitch and step must be well maintained.
Routing Congestion - The routing congestion removal is done by analyzing the routing
congestion and need to increase macro spacing accordingly to get the congestion to lowest
value

IC CompilerFloor planningPower PlanningRouting CongestionPhysical Design

Jet inks

CSE

Jul 2014 – Jan 2017 · 2 yrs 6 mos · Kolar Area, India

Allocating work to engineers & Work status updating to management. Maintaining good Relationship with Clients.

Nokia india pvt ltd

Hardware Test Engineer

Aug 2011 – Sep 2012 · 1 yr 1 mo · Greater Chennai Area

Hardware testing in mobiles (BUI-Basic User Interface testing) like: Audio,RF testing,Camera,Display,keyboard GSM&NSM, Bluetooth etc.
Reducing MFR (Manufacture failure rate) .
Reducing Production Downtime.