Sonal Gawande

Software Engineer

Bengaluru, Karnataka, India7 yrs 11 mos experience

Highly Stable

Key Highlights

7 years of experience in DFx TAP iJTAG RTL integration.
Expert in DFx validation and IEEE 1687 standard.
Proven ability to develop comprehensive test plans.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in DFx and RTL integration.

Contact

Skills

Core Skills

TapDfx Rtl IntegrationDfx VerificationTest Planning

Other Skills

ijtagPerl AutomationSystem on a Chip (SoC)Synopsys toolsTessentVCLPStatic ChecksICLPDLRegression TestingSystemVerilogRTL CodingEngineeringApplication-Specific Integrated Circuits (ASIC)Field-Programmable Gate Arrays (FPGA)

About

Result-oriented DFx-DV engineer, execution-driven and dynamic individual with 7 (including 9 months of internship in the same company) years of experience in DFx TAP iJTAG RTL integration and DFx validation. Thorough understanding of IEEE 1687 standard, SIB network and associated TDRs. Designing iJTAG topology network for a given RTL and implementing it through Tessent and defacto Tool. Understanding the Verification of various domain modules across IP (including TAP JTAG), Sub-System and SoC. Developing test plans, test environment and random and directed test cases. Highly motivated individual with an excellent academic background.

Experience

7 yrs 11 mos

Total Experience

3 yrs 10 mos

Average Tenure

3 mos

Current Experience

Amd

Senior Silicon Design Engineer

Feb 2026 – Present · 3 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

3 roles

SoC Design Verification Engineer (DFx)

Nov 2023 – Feb 2026 · 2 yrs 3 mos · Bengaluru, Karnataka, India · On-site

DFx RTL Integration :
Designing and Implementing TAP iJTAG 1687 network for given RTL.
Understanding the design and Test requirements from IP and SoC teams and coming up with a TAP network based on same.
Getting the TAP network reviewed with respective stakeholders and implementing feedback, if any.
Generation of TAP iJTAG modules (SIBs and TDRs) through Tessent tool and integrating the same in RTL using defacto tool.
Placing the generated TAP components in proper power domains, based on the partition’s power domain.
Placing proper isolations between generated components based on VCLP (VC Low Power check) tool report.
Taking care of all static checks during RTL integration like VC Lint and SpyGlass checks like CDCs (Clock Domain Crossings) and RDCs (Reset Domain Crossings).
Providing accurate Test SDCs (Synopsis Design Constraints) to BE team
Providing ICLs, PDLs, TAP spec files to Component Debug teams.
Implementing BE feedback, if any.
Preparing detailed documentation of related DFT specifications.

TAPijtagDFx RTL Integration

SoC DFT Engineer

May 2019 – Nov 2023 · 4 yrs 6 mos · Bengaluru, Karnataka, India · On-site

DFx Verification :
Involved in Pre-Silicon validation/ verification of DFx IPs such as process and voltage variation monitor IPs, duty-cycle, TAP IP and clock skew measuring IPs of very high-speed clocks and speed-path debug IPs
Developing test plans based on IP functionality and inputs from Post-Silicon teams
Developing test environment, which varies across the projects and the DUTs (SoC or Core)
Writing test cases in Specman or System Verilog to test the connectivity of the IPs in the DUT (SoC or Core)
Running regressions and debugging RTL using Synopsys Verdi tool
Analyzing test results, filing bug reports and verifying RTL/ bug fixes
Preparing detailed documentation, including DFT specifications, test plans and reports.

Test PlanningPerl AutomationDFx Verification

Graduate Technical Intern

Jul 2018 – Apr 2019 · 9 mos · Bengaluru, Karnataka, India · On-site

Learned the DFx test flow for IPs in SoC and Core
Understanding and supporting development of test environment and test cases for the process variation monitor IPs
Learned to use Synopsys Verdi tool and VCS tool

System on a Chip (SoC)Synopsys tools