Sreega Ramasubramanian

Software Engineer

Bangalore Urban, Karnataka, India7 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI verification with strong debugging skills.
Led a sub-team for power management verification.
Proficient in multiple programming languages for testing.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in VLSI and post-silicon testing.

Contact

Skills

Core Skills

Very-large-scale Integration (vlsi)SystemverilogVlsi Verification

Other Skills

C++JTAGPCIe ControllerVerdiOpen Verification MethodologyPythonPerlObject-Oriented Programming (OOP)Test PlanningScriptingAdvanced C++ClockingGate Level SimulationUniversal Verification Methodology (UVM)System Verilog Assertion

About

Experienced VLSI Verification Engineer with a demonstrated history of working in the modules GLS, ICC POWER, and DFX Verification. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Very-Large-Scale Integration (VLSI), System Verilog Assertion, Python (Programming Language), and Perl scripting. Strong engineering professional with a Bachelor's degree focused in Electrical and Electronics Engineering from Karpagam College of Engineering.

Experience

7 yrs 11 mos

Total Experience

3 yrs 11 mos

Average Tenure

4 yrs 8 mos

Current Experience

Amd

2 roles

Senior Silicon Design Engineer

Promoted

Dec 2023 – Present · 2 yrs 5 mos

Coding testcases in c++. Worked in jtag for single and multi die ie iod and pkg. on post silicon, worked on jtag, ring oscillator, axis, test transistor .
Currently working on pcie controller post silicon.

C++JTAGPCIe ControllerVery-Large-Scale Integration (VLSI)SystemVerilog

Silicon Design Engineer 2

Sep 2021 – Dec 2023 · 2 yrs 3 mos

Work in server soc dfx team. Coding testcases in c++.

C++VerdiJTAGVery-Large-Scale Integration (VLSI)SystemVerilog

Wipro limited

VLSI Verification Engineer (Intel Client)

Jun 2018 – Sep 2021 · 3 yrs 3 mos · Bengaluru, Karnataka

SOC Functional Verification
1. I have worked in GLS(gate level simulation),Integrated clock controller(ICC) and power module for Intel client(Platform Controller Hub).
2. Found various Testbench,RTL and PMC(power management ARC controller) Firmware bugs in power and icc. I was appreciated by the clients for prompt and quick debugs and closingon priority works.
3. I wrote python and perl scripts to ease the debugs in project and seq generation.
4. Leading sub team :- I also played sub lead role (8 members) for Power by monitoring the pass percentage of testcases, allocating tasks, monitoring and guiding them with debugs.
5. As a sub - lead of power team for new project, I saw to it that the priority bugs are closed on time and closed on the deadlines on time.

Open Verification MethodologyPythonPerlVLSI VerificationSystemVerilog