Sean Sequeira

Engineering Manager

Bengaluru, Karnataka, India23 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 20+ years in VLSI design and verification
  • Led teams of 40+ engineers across multiple projects
  • Expertise in mixed-signal and digital domains
Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in VLSI and mixed-signal design.

Contact

LinkedIn

Skills

Core Skills

VlsiDesignFunctional VerificationIp ManagementMixed-signal VerificationIntegrationVerificationDigital DesignMixed-signal DesignSoc Design

Other Skills

DDR PHY IPFirmwareDMA ControllersEthernet IPsQuality AssuranceDFx verificationDDR PHYSubIP integrationFunctional coverageBug trackingDigital IPsMixed-signal IPsTools and methodologyPLLsMixed-signal integration

About

- 20+ years of experience in VLSI design/verification during which I worked in digital, analog and mixed-signal domains - Functioning as manager/leader for IP design/verification/firmware teams of 40+ engineers (full-time and contractors) - Experienced in people management, vendor management, hiring, detailed project planning & tracking with focus on high quality, flawless execution - Worked with cross-geo, cross-functional teams, and mentored team on handling challenges effectively - Experienced in taking up pilot projects, setting up teams from scratch, and instilling a collaborative, high performing & result-oriented culture - Handled complex ASIC/FPGA IPs like Memory Hard IPs, Memory controllers, Ethernet IPs,... and worked in IP, Sub-system and SOC levels - Exposed to behavioral modeling, IO characterization and generation of .lib files - Exposed to STA, Synthesis, writing ECO and PERL scripts, Equivalence checking, RTL coding in VHDL & Verilog, Linting, and verification using ARM assembly - Experienced in Synopsys, Mentor Graphics and Cadence (limited exposure) based mixed-signal co-simulation flows for functional verification - Expertise in various aspects of logic/functional verification like DTP (detailed test plan) creation including testbench architecture definition, RTL/Gate/Power-aware verification, SPICE or Verilog-AMS based mixed-signal verification, Coverage, Regressions, Debug - Experienced in VHDL, Verilog and System Verilog (UVM/VMM) based verification environment - Experienced in defining customer-centric flows like Nanosim-VCSMX based mixed-signal verification flow for TI-Advanced Embedded Control (TI-AEC) group - Exposed to correlating silicon data to simulations using mixed-signal co-simulation flow

Experience

23 yrs 8 mos
Total Experience
4 yrs 9 mos
Average Tenure
9 yrs 1 mo
Current Experience

Intel corporation

4 roles

Engineering Manager

Mar 2024 – Present · 2 yrs 1 mo · Bengaluru, Karnataka, India

  • Part of CEG (Client Engineering Group) DDRPHY IP team. Operating as senior manager and Bangalore site lead for the DDR PHY IP team leading Front End Design, Verification & Firmware teams of 40+ engineers. Responsible for flawless execution of front-end aspects of DDR PHY IP (Design, Verification and Firmware) to ensure timely, high quality delivery of cutting edge, next generation DDR PHY IPs to the Memory Controller Sub-System and SOC
VLSIDDR PHY IPDesignVerificationFirmware

Engineering Manager

Promoted

Jan 2022 – Mar 2024 · 2 yrs 2 mos · Bengaluru, Karnataka, India

  • Part of IPSE (IP Solutions Engineering) team in PSG (Programmable Solutions Group), Intel. Operated as senior manager for team of 25+ engineers, with the charter being Functional verification of DMA Controllers, Reset Controllers and Ethernet IPs, delivered on time and with high quality to external customers through QPDS (Quartus Prime Design Software). Worked as IP owner for Ethernet IPs, leading design & verification teams to deliver IPs meeting schedule and quality requirements. Served as single point of contact (SPOC) while managing/leading a team of design & verification engineers delivering IPs from Bangalore site into multiple critical PSG projects
Functional verificationDMA ControllersEthernet IPsQuality AssuranceFunctional VerificationIP Management

Engineering Manager

Promoted

Jul 2017 – Dec 2021 · 4 yrs 5 mos · Bengaluru, Karnataka, India

  • Part of MIG (Mixed-Signal IP Solutions Group) Verification team. Operated as senior manager for the DDR PHY verification team of 15+ engineers, with the charter being Functional and DFx verification of DDR PHY, delivered on time and with high quality to the Memory Controller Sub-System and SOC
Functional verificationDFx verificationDDR PHYFunctional VerificationMixed-Signal Verification

Engineering Manager

Jan 2017 – Jun 2017 · 5 mos · Bengaluru, Karnataka, India

  • Had a brief stint in CIG (Chipsets and IP Technologies Group) Verification team, where I worked on SCS (Storage and Communication Sub-System) and LPSS (Low Power Sub-System), and was responsible for subIP integration (RTL and Verif collaterals) and bring-up, functional coverage plan definition and implementation leading a team of 2 engineers, contractor task assignment, tracking, mentoring, IP/SOC engagement, bug tracking
SubIP integrationFunctional coverageBug trackingIntegrationVerification

Microchip technology india pvt. ltd.

Principal Engineer

Dec 2013 – Jan 2017 · 3 yrs 1 mo · Bangalore

  • Part of MCU32 (32 bit microcontrollers) IP Verification team. Operated as Verification Lead, and was responsible for verification of digital IPs like Cache controller, Memory controller, 10/100Mbps Ethernet MAC, SD2.0 Host Controller, using SV-VMM testbench, identifying and porting appropriate tests from IP level to SOC level for integration verification, defining QADMS based mixed-signal verification flow at IP level, enhancements to existing flow to improve RTL and TB check-in quality, setting up cron based daily regression runs to report pass-rate, functional and code coverage numbers for transparent tracking of verification progress on a daily basis. Briefly responsible for UPF based power-aware RTL simulations at SOC level. Participated in Microchip Verification Council meetings where flow and methodology related items are discussed and rolled out.
VerificationDigital IPsMixed-signal verificationDigital Design

Amd

2 roles

Member of Technical Staff

Promoted

Nov 2010 – Dec 2013 · 3 yrs 1 mo

  • Verification lead and owner for macros like PLLs, Voltage regulator, Clock stretcher, voltage monitors. Also responsible for tools and methodology for mixed-signal IPs. Involved in functional verification of MIPIDSI PHY.
Functional verificationMixed-signal IPsTools and methodologyFunctional VerificationMixed-Signal Design

Senior Design Engineer

Feb 2008 – Oct 2010 · 2 yrs 8 mos

  • Responsible for verification of PLLs. Pioneered PLL verification at AMD, India and helped grow the team to own verification of almost all PLLs at AMD.
VerificationPLLsMixed-signal IPsMixed-Signal Design

Pmc-sierra

Mixed Signal Verification Engineer

Jan 2007 – Feb 2008 · 1 yr 1 mo

  • Responsible for mixed-signal integration and verification of SERDES and IO characterization. Pioneered mixed-signal integration and verification at PMC Sierra, India. Ramped up quickly and helped build the team in India (full-time engineers and service providers) to take up complete ownership and execute projects independently.
VerificationMixed-signal integrationSERDESMixed-Signal Design

Wipro technologies

Module Leader

May 2002 – Jan 2007 · 4 yrs 8 mos

  • Responsible for various things: SOC level verification, IP level verification, STA, Synthesis, ECO scripts, RTL coding, SPICE simulations of first generation on-chip VREG, behavioral modeling. Proposed and defined Nanosim-VCSMX based mixed-signal simulation flow for TI-AEC (Advanced Embedded Controllers) SOCs.
SOC verificationSTASynthesisVerificationSOC Design

Dell

Technical Support

Feb 2002 – Apr 2002 · 2 mos

  • Responsible for phone support of Dell desktops.

Education

Sri Jayachamarajendra College of Engineering

BE — Electronics & Communication

Jan 1996 – Jan 2001

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