Ashish Yadav

Software Engineer

Jalandhar, Punjab, India1 yr 11 mos experience

Key Highlights

  • Experienced in CPU physical design at Intel.
  • Strong foundation in VLSI design from NIT Jalandhar.
  • Proficient in digital IC design methodologies.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in digital IC design and physical design methodologies.

Contact

LinkedIn

Skills

Core Skills

Physical DesignDigital Ic Design

Other Skills

PlacementRoutingClock Tree SynthesisTCL scriptingFloorplanningSignal IntegrityPlacement and RoutingStatic Timing AnalysisTiming ClosureCircuit DesignCMOSVerilogCadence VirtuosoXilinx Vivado

Experience

1 yr 11 mos
Total Experience
1 yr 11 mos
Average Tenure
1 yr 11 mos
Current Experience

Intel corporation

2 roles

CPU Physical Design Engineer

Jun 2024 – Present · 1 yr 11 mos

Physical DesignPlacementRoutingDigital IC Design

Intern

Jun 2023 – May 2024 · 11 mos

Clock Tree SynthesisTCL scripting

Education

Dr. B R Ambedkar National Institute of Technology, Jalandhar ( PUNJAB)

Master of Technology - MTech — VLSI Design

Aug 2022 – Jun 2024

KRISHNA INSTITUTE OF ENGINEERING AND TECHNOLOGY, GHAZIABAD

Electrical — Electronics and Communications Engineering

Jawahar Navodaya Vidyalaya - JNV

Stackforce found 100+ more professionals with Physical Design & Digital Ic Design

Explore similar profiles based on matching skills and experience

TS

Tanmay Sahu

Physical Design Engineer

at Intel Corporation

Bhopal, India1 yr 11 mos exp
RL

Rushikesh Landge Patil

Physical Design Engineer

at Syntiant Corp.

Bengaluru, India2 yrs 9 mos exp
Very-Large-Scale Integration (VLSI)
Sahil Srivastava

Sahil Srivastava

SoC Design Intern

at Intel Corporation

Delhi, India0 mo exp
DFTElectronic EngineeringDigital Electronics
Soumadeep Das

Soumadeep Das

Silicon Design Engineer

at AMD

Bengaluru, India1 yr 11 mos exp
Universal Verification Methodology (UVM)SystemVerilog
Hareesh Kanneboina.

Hareesh Kanneboina.

Senior Engineer

at MediaTek

Bengaluru, India2 yrs 10 mos exp
SynthesisSTA & Timing ECOsConformal LEC
Shruti Srivastava

Shruti Srivastava

Graduate Technical Intern

at Intel Corporation

Noida, India0 mo exp
RTL Design
Pradhi Kumar

Pradhi Kumar

ASIC Engineer

at NVIDIA

Bengaluru, India3 yrs 10 mos exp
Static Timing Analysis
Niranjan Kumar

Niranjan Kumar

Design Evaluation engineer

at Analog Devices

Bengaluru, India8 yrs 3 mos exp
Analog Circuit DesignAnalog Integrated Circuit Design