Sakthieswaran P.

Software Engineer

Bengaluru, Karnataka, India26 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 11 years in Digital ASIC verification.
  • Expertise in processor-based SoC verification.
  • Involved in full chip verification for multiple tape outs.
Stackforce AI infers this person is a Digital ASIC Verification Expert with a focus on SoC and processor-based architectures.

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Skills

Other Skills

RTL designSoCFunctional VerificationAMBA AHBTCLARMLow Power VerificationEDAIntegrated Circuit DesignLow-power DesignICDigital Signal ProcessorsDebuggingVLSIVerilog

About

• Around 11 years experience in Digital ASIC verification • Strong background in processor based SOC Verification. • Good exposure to ARM cores, DSP cores & Processor subsystems. • Involved in Full Chip Verification for more than 4 Tape outs. Expertise Highlights ---------------------------- • Chip infrastructure like clocking and Reset scheme verification • Low power verification methodologies using CPF/UPF • Processor env setup, boot & familiarity to debug infrastructure • Familiar with power estimation techniques • Familiar to security architectures • Exposure to AMBA protocols • ARM subsystem integration verification • Digital Signal Processor(DSP) core, L1 cache design & verification

Experience

26 yrs 7 mos
Total Experience
5 yrs 3 mos
Average Tenure
10 yrs 8 mos
Current Experience

Intel corporation

2 roles

Principal Engineer

Promoted

Nov 2023Present · 2 yrs 6 mos

Lead Verification Engr.

Sep 2015Present · 10 yrs 8 mos

  • Subsystem/IP Verification

Qualcomm

Staff Engineer

Jan 2013Aug 2015 · 2 yrs 7 mos · Bangalore

  • PM verification at SOC

St microelectronics

Staff Engineer

May 2009Dec 2012 · 3 yrs 7 mos · Bangalore

  • SOC Verification of DTV Chips

St ericsson

Tech Lead

Jan 2009Apr 2009 · 3 mos · Bangalore

  • SOC verification

Nxp

2 roles

Tech Lead

Promoted

Jan 2006Dec 2008 · 2 yrs 11 mos

  • SOC verification & Design

Design Engr

Feb 2001Dec 2005 · 4 yrs 10 mos

  • DSP processor & Cache design & verification

Tata steel

Graduate Trainee

Jan 1996Jan 1998 · 2 yrs

  • Project Gopalpur

Education

Indian Institute of Technology, Madras

M.Tech — Electrical Engineering

Jan 1999Jan 2001

Birla Institute of Technology and Science, Pilani

B.E.(Hons) — Instrumentation

Jan 1992Jan 1996

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