Saswat Padhy — Software Engineer

Low Power Design Engineer with good understanding & experience in -ASIC low power design and implementation across mobile, compute ,XR/AR/VR GPUs -Understanding of GPU & processor architecture[ARM/RISC-V] with AMBA protocols[AHB/AXI] & memory subsystems -Power characterization using PTPX/Power Artist for various GPU cores for different GPU benchmarks -Participate in defining power management schemes and low power modes like clock gating, power gating, DVFS, voltage islands etc. -Explore power optimization opportunities in RTL with Power Artist/ RTL-A for enhanced PPA -Create power specifications ,UPF definition & power intent validation using CLP -Experience in digital design of low-power IPs with Verilog -Perform power estimation, roll, up and tracking through all phases of the project using PTPX -Explore power optimization opportunities & suggest ways to improve power, and drive PPA convergence. -Experience with ASIC low power aware synthesis , LEC/FM non-equivalence debugs -Participate in pre/post-silicon power co-relation & debugs -Understanding of timing critical paths analysis using Prime-time -scripting with tcl/python

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in low power design and optimization.

Location: Bengaluru, Karnataka, India

Experience: 6 yrs 11 mos