Sreekanth Mapu

Software Engineer

Bengaluru, Karnataka, India12 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 10 years of experience in Physical Design.
Led multiple subsystem projects at Qualcomm.
Expertise in advanced tech nodes from 28nm to 5lpe.

Stackforce AI infers this person is a Physical Design Engineer with extensive experience in semiconductor design and implementation.

Contact

Skills

Core Skills

Physical DesignStatic Timing AnalysisClock Tree Synthesis

Other Skills

Low-power DesignCadence Encounter

About

-> Having 10+ years of experience in Physical Design. -> First 3 yrs worked in Sicon & Altran. Was working for Qualcomm & LG for clients. -> Next 7yrs worked in Qualcomm as a full time. Was involved in 10+ projects. Experience on subsystem level floorplan and placement with multiple trials for convergence. Experience on subsystem level CTS -> PRO. Which is having more than 150+ clocks Experience on subsystem level / block level STA. Experience in Leading the sub system. -> Experience in Innovus, FC , PT and Tempus. -> Worked on tech nodes of 28nm, 14nm, 11nm , 7ff , 8lpe, 5lpe, 4ff, 3lpe

Experience

12 yrs 1 mo

Total Experience

4 yrs

Average Tenure

8 yrs 11 mos

Current Experience

Qualcomm

3 roles

Staff Engineer

Promoted

Dec 2023 – Present · 2 yrs 4 mos · On-site

Working as subsystem lead.

Low-power DesignCadence EncounterStatic Timing AnalysisClock Tree SynthesisPhysical Design

Senior Lead Engineer

Nov 2020 – Dec 2023 · 3 yrs 1 mo · On-site

> Worked on subsystem level CTS runs to ECO implementation.
> Number of clocks will be 150+
> Worked on STA for one of the subsystem ; which is having 7 sub_hms inside and subsystem top.
> Worked on subsystem level lead for PnR implementation.

Clock Tree SynthesisStatic Timing AnalysisPhysical Design

Senior Engineer

May 2017 – Nov 2020 · 3 yrs 6 mos · On-site

Worked on subsystem level floorplan and placement.
> 300+ macros & 6M inst count.
> 150+ clocks
> Worked on multiple projects floorplan & placement for the subsystem.
> Worked on many floorplans for the convergence.

Physical DesignStatic Timing Analysis

Altran india

Physical Design Engineer

Sep 2015 – Apr 2017 · 1 yr 7 mos · Bangalore · On-site

Worked as a consultant in Qualcomm.
Block level implementation from floorplan to GDS

Physical Design

Sicon design technologies pvt. ltd.

Physical Design Engineer

Jan 2014 – Aug 2015 · 1 yr 7 mos · Bangalore · On-site

Worked as a Consultant in Qualcomm and LG soft India
Worked fullchip activities in Qualcomm.
Worked on Video block in LG for Floorplan to GDS.

Physical Design

Education

Birla Institute of Technology and Science, Pilani

M.tech — VLSI

Jun 2017 – Jul 2019

Jawaharlal Nehru Technological University

Bachelor of Technology (B.Tech.) — Electrical and Electronics Engineering

Jan 2009 – Jan 2013

ABV junior college, Jangaon

Intermediate — MPC

Jan 2007 – Jan 2009

Zilla parishath High school, Bondugula

SSC

Jan 2006 – Jan 2007

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