Darshal Patel

Software Engineer

Vadodara, Gujarat, India18 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT engineering with extensive SOC experience.
Proficient in multiple design tools for chip validation.
Strong background in test architecture for complex chips.

Stackforce AI infers this person is a DFT engineer with expertise in semiconductor design and testing.

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Skills

Other Skills

VerilogCadence VirtuosoMatlabVLSIXilinx ISEVHDLXilinxFPGALTSpiceSPICECComputer ArchitectureCircuit DesignAnalog Circuit DesignIntegrated Circuit Design

About

I am tech enthusiast and quick learner. I am pursuing my career as DFT engineer. I am responsible for adding test circuits to make designs testable. In my career as DFT engineer, I have worked on SOC level chip for full flow stating from test insertion to silicon validation. I have worked on multiple Avago chips for test vector generation activities. I have worked on a sensor chip which had specific requirement for pin limited testing. I have worked on multiple design tools. Cadence: RTL compiler, Encounter test, Encounter True Time, NCSim, LEC. Mentor Graphics: Tessent, TestKompress(EDT), FastScan Synopsys: Design Compiler, TetraMax, Virage

Experience

18 yrs 5 mos

Total Experience

3 yrs

Average Tenure

6 yrs 9 mos

Current Experience

Qualcomm

2 roles

Staff Engineer

Promoted

Nov 2022 – Present · 3 yrs 6 mos · Bengaluru, Karnataka, India

Senior Lead Engineer

Aug 2019 – Nov 2022 · 3 yrs 3 mos · Bengaluru, Karnataka, India

Amd

2 roles

Senior Design Engineer

Jul 2018 – Jul 2019 · 1 yr · Bengaluru Area, India

Design Engineer

Oct 2016 – Jul 2019 · 2 yrs 9 mos · Bengaluru Area, India

Working in CT-IP team as DFT engineer.

Einfochips

DFT Engineer

Oct 2015 – Oct 2016 · 1 yr · Ahmedabad, Gujarat

My responsibility in E-infochips is to take part in DFT Architecture design and in Pattern generation related activities. I worked on a sensor chip which had stringent pin limitation. We implemented Cadence "SmartScan" architecture to add deserializer-serialzer architecture over the existing compression to reduce the test pin requirements. I was responsible for adding architecture for making at-speed testing feasible. I also did pattern generation and validation for at-speed test. I worked on Pattern generation activity for two chips. In this project I was responsible for handling JTAG tests(both AC and DC), PMRO test, Efuse test, serdes test and PLL tests for pattern generation and validation activity.

Open-silicon

ASIC Design Engineer

Jul 2013 – Oct 2015 · 2 yrs 3 mos · Bangalore

I worked in Open-Silicon for DFT domain for 2.5 years. I completed a SOC level tape out in May,2015. It was 10 Million gate chip for networking application. I did DFT implementation starting from MBIST, SCAN insertion and pattern generation for 6 blocks. Also, I worked on top level scan hookup. I did top level pattern generation for stuck-at as well as transition faults. I also worked on IP tests for PLL, Synopsys DDR2-3Lite and ARM L1MBIST. The chip I worked on got taped out and I did post tape out activities which completed successfully and it reached to production phase.

Da-iict

Teaching Assistant and Student

Aug 2011 – May 2013 · 1 yr 9 mos · Gandhinagar, Gujarat

I pursued my M.Tech in VLSI and Embedded Systems here. I did my thesis on Power Shutoff Technique on MIPS processor. It included designing the power control unit and shutting the CPU on every NOP operations. Along with the coursework I was responsible for conducting Labs for undergraduate students.