Pooja Shinde

Product Engineer

Bengaluru, Karnataka, India9 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Static Timing Analysis for semiconductor design.
  • Proficient in multiple CAD tools for VLSI design.
  • Strong foundation in Electronics and Communication Engineering.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in STA and VLSI CAD tools.

Contact

vpoojashinde@gmail.comLinkedIn

Skills

Core Skills

Static Timing Analysis

Other Skills

Microsoft OfficeMicrosoft ExcelManagementCC++CadenceCadence VirtuosoCadence EncounterCadence Virtuoso Layout EditorXilinx ISEVerilogVLSI CADModelSimMatlabElectronics

Experience

9 yrs 2 mos
Total Experience
3 yrs 5 mos
Average Tenure
8 yrs 10 mos
Current Experience

Samsung india

STA Engineer

Jan 2022 – Present · 4 yrs 4 mos

Static Timing Analysis

Intel corporation

STA Engineer

Aug 2021 – Dec 2021 · 4 mos · Bengaluru, Karnataka, India

Static Timing Analysis

Si2chip technologies pvt. ltd.

2 roles

Design Engineer

Promoted

Mar 2019 – Present · 7 yrs 2 mos

Associate Design Engineer

Jul 2017 – Feb 2019 · 1 yr 7 mos

Qualcomm

STA Engineer

Jul 2018 – Dec 2020 · 2 yrs 5 mos · Bengaluru, Karnataka, India

Static Timing Analysis

Sion semiconductors private limited

FPGA Design Intern

Dec 2016 – Apr 2017 · 4 mos · Bengaluru, Karnataka, India

Education

Vellore Institute of Technology

Master of Technology (M.Tech.) — VLSI Design

Jan 2015 – Jan 2017

Savitribai Phule Pune University

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 2011 – Jan 2015

Kendriya Vidyalaya

SSC — HSC

Jan 2000 – Jan 2011

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