Siva kumar T S

Software Engineer

Bengaluru, Karnataka, India16 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and VLSI methodologies.
Proven track record in timing closure and formal verification.
Strong background in CPU and GPU design integration.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and ASIC development.

Contact

Skills

Core Skills

Physical DesignVlsi

Other Skills

FloorplanPower-grid generationPlace & routeClock tree synthesisTiming ECOsFixing DRC & LVSFormal verificationCrosstalk glitch analysisExtractionTiming closureIR analysisStatic Timing AnalysisASICSoCTCL

About

The work starts at Netlist handoff and does all aspects of design flow. Developed next-generation CPU,GPU designs. Responsible for creating/integrating the physical database to be eventually sent to the fab to be manufactured. Work on layout/physical design, floor planning, synthesis, place and route, reliability check, noise analysis, power analysis, manufacturability check, integration of custom circuits, clock implementation. Validating design and micro-architectural implementation and assumptions. STA , DRC/DRC+, Litho Checks,Formal equivalence verification, LVS. Developing solutions to problems utilizing formal education and judgment Automating design tasks in order to complete the block in the most efficient and expeditious fashion possible. Specialties: STA ,IR Analysis

Experience

16 yrs 10 mos

Total Experience

3 yrs 8 mos

Average Tenure

4 yrs 10 mos

Current Experience

Capgemini engineering

Lead Engineer

Jul 2021 – Present · 4 yrs 10 mos · Bengaluru, Karnataka, India

Aricent n.a. inc.

Lead Engineer

Jan 2020 – Jul 2021 · 1 yr 6 mos · Hudson, Massachusetts, United States

Aricent

Lead Engineer

Feb 2013 – Jan 2020 · 6 yrs 11 mos · Bengaluru Area, India

Netlist to GDS implementation of two blocks. It includes floorplan, power-grid generation, place & route, clock tree synthesis, timing ECOs, fixing DRC & LVS, formal verification, crosstalk glitch analysis, extraction and timing closure, IR analysis.

FloorplanPower-grid generationPlace & routeClock tree synthesisTiming ECOsFixing DRC & LVS+7

Soctronics

P & R Engineer

Jul 2009 – Feb 2013 · 3 yrs 7 mos

Netlist to GDS implementation of blocks. It includes floorplan, power-grid generation, place & route, clock tree synthesis, timing ECOs, fixing DRC & LVS, formal verification, crosstalk glitch analysis, extraction and timing closure, IR analysis.

FloorplanPower-grid generationPlace & routeClock tree synthesisTiming ECOsFixing DRC & LVS+7

Amd

Physical Design Engineer (consultant)

Jul 2009 – Mar 2011 · 1 yr 8 mos

worked on 28nm,32nm,40nm designs.
worked on Cadence, Synopsys ,Mentor tools.
Carried out block level floorplan, placement, CTS, optimization, routing, timing closure.
Employee of SoCtronics.