Abhishek Puttaswamy — Software Engineer

Programming/Scripting: Verilog, System Verilog, C/C++/OOP, TCL, Python, Perl. Tools: VCS, QuestaSim, IC Compiler, Cadence Virtuoso, Primetime, Synopsys DC, MATLAB, Perforce. GIT Skills: UVM, Assertions, Constraint randomization, Logic design, Static timing analysis (STA). SPI protocol, APB, AIB. INTEL CORPORATION SoC Design Engineer Working on Design verification and Integration of SoC. Enablement of transceiver tile for FPGA. Involved in development of Design Verification architecture, Testbench environment, Test plan development, Test case writing, Coverage, Reference model integration using DPI C, debugging, enabling regressions flow, Revision control.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SoC and ASIC development.

Experience: 10 yrs