Jan 2025 – Feb 2026 · 1 yr 1 mo · India · On-site

Oct 2020 – Jan 2025 · 4 yrs 3 mos · Bengaluru

• DV lead for HSIO in the mobile SOC, responsible for USB2/3, PCIE gen 3, UFS 4 subsystem verification.

Jun 2014 – Oct 2020 · 6 yrs 4 mos · Bangalore

• DV lead on L2 switch (SDN). Design was from scratch using SDN, built the OVM TB environment, owned the DV for ingress parser module.

Dec 2012 – Jun 2014 · 1 yr 6 mos · Bangalore

• Worked on Serdes integration Subsystem.

Jun 2010 – Dec 2012 · 2 yrs 6 mos · Bangalore

• Verification Architect for the Mixed Signal Verification of 28G Serdes Core using UVM, development of Testbench Environment from Scratch.
• Verification ONFI3.0 compliant Nand Flash Phy using OVM, development of the tb-env from scratch.

Sep 2009 – Jun 2010 · 9 mos

• Worked as a technical lead for the Digital aspect(RTl to Timing Analysis) of the Gyro Chipset of the ECU.
• Conceptualization and implementation of constrained-random-coverage based verification methodology using system-verilog in the place of the existing VHDL testbench and had sucess with multiple bugs uncovered on a taped-out ASIC using the above methodology.

Mar 2007 – Sep 2009 · 2 yrs 6 mos · Vorarlberg, Austria · On-site

• I work as an individual contributor here and have handled the following activities for the past 1.5years :
• a] Synthesis-using DC for a 90nm ASIC
• b] Development of Fixed point digital filters (LPF, HPF, BPF) for an audio sensor ASIC in Matlab and Verilog.
• c] At-Speed-LOC-DFT using Tmax for a 90nm ASIC
• d] Worked on Architecture Design , Verification, DFT of a 0.4 micron automotive ASIC

Jun 2006 – Feb 2007 · 8 mos

• Verification of the Graphic Memory Controller Hub ASIC with Intel's legacy verification environment.

Mar 2005 – Apr 2006 · 1 yr 1 mo

• Verification of the DTV ASIC that involved processing of the DTV I/Q samples after reception through Time/Frequency domain equalization till the Convulutional/Block FEC correction. Was leading a team of 5 Engineers.

Jun 1997 – Mar 2005 · 7 yrs 9 mos

• Started as a Verification Engineer and consulted for Cisco systems for their networking ASIC's, moved on to the role of a Project Manager in the Conexant Account which later was spun off in to Skyworks. Was responsible for verification, synthesis, dft, sta of their re-spins of the baseband receiver ASIC and GPS ASIC. Was leading a team of 7 to 12 Engineers over a period of 3 years.