Prafull Geed

Software Engineer

Bengaluru, Karnataka, India3 yrs experience
Highly Stable

Key Highlights

  • Hands-on experience in analog circuit layout design.
  • Proficient in multiple programming languages including Python and Perl.
  • Strong debugging skills with knowledge of DFT.
Stackforce AI infers this person is a VLSI Engineer with expertise in layout design and verification.

Contact

LinkedIn

Skills

Core Skills

PdkCheckoutLayout VerificationAnalog Circuit Design

Other Skills

VerilogSystemVerilogPerl scripting languageCAD automationLayout designDRCLVSParasitic ExtractionSKILL programmingCadence VirtuosoComponent DesignDebuggingPython (Programming Language)Perl AutomationLinux

About

As a Graduate Technical Intern in the Layout Verification domain at Intel Corporation, I possess hands-on experience in designing analog circuit layouts and conducting design verification of circuit layouts. I have a proficient understanding of RC-extraction and am skilled in using the C language, Python, and Perl scripting languages. Additionally, I have strong debugging skills and knowledge of DFT. At present, I am working on automation of LV domain using the Perl scripting language, gaining practical exposure in CAD automation with the SKILL programming language. Moreover, I am well-versed in Digital Electronics, Verilog, System Verilog, and Computer Architecture.

Experience

3 yrs
Total Experience
3 yrs
Average Tenure
3 yrs
Current Experience

Intel corporation

2 roles

PDK Engineer

Jun 2023 – Present · 2 yrs 11 mos · Bengaluru, Karnataka, India · On-site

CheckoutPDK

Graduate Technical Intern

Aug 2022 – May 2023 · 9 mos · Bengaluru, Karnataka, India · On-site

  • Worked on LV domain automation using Perl scripting language and CAD automation using SKILL programming
  • Hands-on experience in Layout desing using Virtuoso (have made layouts of all logic gates AND, OR, NOT, NAND, and NOR)
  • Layout Verification (DRC, LVS) using Calibre and IC-Validator
  • Parasitic Extraction
VerilogSystemVerilogPerl scripting languageCAD automationLayout designLayout Verification+4

Chegg inc.

Chegg Q/A Expert

Apr 2021 – Feb 2022 · 10 mos

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI Design

Jan 2021 – Jan 2023

Ujjain Engineering College, Sanwer Road, Ujjain

Bachelor of Engineering - BE — Electrical Engineering

Jan 2016 – Jan 2020

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