Rakesh Ranjan — CEO
Experience in MBIST and DFT verification (test pattern simulation ) for SOC Automatic Test pattern Generation(ATPG) ,Test coverage analysis/improvemnet and test pattern simulation. Experience in DFT implementaion and scan insertion. Have also done the LEC for pre and post MBIST inserted netlist using the tools LEC conformal. Have also done the timing checks (using DC )and analysed the violation.
Stackforce AI infers this person is a VLSI Design and DFT Verification expert with extensive experience in SoC development.
Location: Bengaluru, Karnataka, India
Experience: 15 yrs 6 mos
Skills
- Dft
- Soc
Career Highlights
- Expert in DFT verification and ATPG for SoC.
- Proficient in static timing analysis and violation analysis.
- Strong background in VLSI design and testing methodologies.
Work Experience
Qualcomm
Senior staff (1 yr 9 mos)
Intel Corporation
SOC Design Engineering Manager (1 yr 11 mos)
DFT Lead Engineer (4 yrs 2 mos)
Freescale Semiconductor
SoC Design Engineer (5 yrs 5 mos)
Wipro Technologies
Project Engineer (2 yrs 3 mos)
Education
Bachelor of Technology (B.Tech.) at West Bengal University of Technology, Kolkata
12th at Loyola High School
10th at Don Bosco Academy
