DHARMAPURI THRIVIKRAM CHAKRADHAR

Product Engineer

Bengaluru, Karnataka, India9 mos experience

Key Highlights

  • Expert in SoC verification and UVM methodologies.
  • Mentors students in Digital Design and Verification.
  • Hands-on experience with RISC-V and APB protocols.
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in semiconductor design and verification methodologies.

Contact

Skills

Core Skills

Soc VerificationDesign VerificationVlsi Design Verification

Other Skills

SystemVerilogUniversal Verification Methodology (UVM)Digital ElectronicsVerilogAMBA APBGPIOComputer SimulationsDigital DesignsRegister Abstraction Layer (RAL)Functional VerificationAssertion-Based Verification (SVA)Coverage-Driven VerificationTestbench DevelopmentSimulationWaveform Analysis

About

Currently working as a Design Verification Engineer at MediaTek, contributing to SoC verification with a focus on RAL-based methodologies. Skilled in SystemVerilog and UVM, I work on building robust verification environments, register modeling, and debugging complex scenarios to ensure functional correctness. My core interests lie in Digital Design and Verification, with continuous learning in UVM, SVA, and advanced SoC verification flows. Alongside my professional work, I actively mentor students in Digital Design, Verilog, SystemVerilog, and UVM through my mentorship program. Always eager to learn, grow, and take on challenging verification problems.

Experience

9 mos
Total Experience
8 mos
Average Tenure
1 mo
Current Experience

Mediatek

Design Verification Engineer

Apr 2026Present · 1 mo · Bengaluru, Karnataka, India · On-site

  • ▫️Currently working on SoC verification onboarding, with focus on Register Abstraction Layer (RAL) concepts and methodology
  • ▫️Learning and understanding UVM-based verification environments and their integration at SoC level
  • ▫️Studying register modeling, sequences, adapters, and predictors in RAL
  • ▫️Exploring SystemVerilog and UVM constructs used in industrial verification flows
  • ▫️Analyzing existing verification environments to understand testbench architecture and data flow
  • ▫️Preparing to contribute to functional verification and debugging in ongoing projects
SystemVerilogUniversal Verification Methodology (UVM)SoC VerificationDesign Verification

Festiva moments

VLSI Design Verification Tutor

Feb 2026Present · 3 mos · Hybrid

Digital ElectronicsVerilog

Maven silicon

3 roles

Intern & Lab Mentor – VLSI Design & Verification

Aug 2025Apr 2026 · 8 mos · On-site

  • ▫️Contributing to RISC-V processor and APB-based UART RTL design and debugging, ensuring functional correctness, timing closure, and protocol compliance.
  • ▫️Guiding trainees in RTL design and verification concepts, ensuring a strong technical foundation.
  • ▫️Supporting hands-on lab sessions by debugging code and resolving simulation/synthesis issues.
  • ▫️Conducting periodic reviews to track trainee progress and provide constructive feedback.
  • ▫️Helping trainees adopt best practices in SystemVerilog, UVM, and standard VLSI workflows.
  • ▫️Mentoring trainees by guiding RTL/verification debugging and reviewing their project implementations.
VerilogSystemVerilogVLSI Design Verification

Design and Verification Internship

May 2025Aug 2025 · 3 mos · On-site

  • Designed and Verified APB based GPIO.
  • ▫️APB Protocol Integration : Designed a GPIO peripheral interface compliant with AMBA APB (Advanced Peripheral Bus) protocol, enabling low-power and simple register-based communication with the system bus.
  • ▫️Configurable I/O Functionality : Implemented bidirectional GPIO ports with programmable direction control and data registers, supporting both input and output operations through APB register writes.
  • ▫️Address Decoding and Register Mapping : Developed address decoder and internal register mapping logic for control/status registers like `DIR`, `DATA_OUT`, `DATA_IN`, and `INT_EN`.
  • ▫️Verification and Simulation : Verified the GPIO module using System Verilog testbench with APB Master model, including directed and random testcases to ensure protocol and functional correctness.
AMBA APBGPIODesign Verification

VLSI Design & Verification Trainee

Apr 2024Apr 2025 · 1 yr · On-site

  • ▫️Designed and implemented complex digital circuits and verified simulations.
  • ▫️Worked on industry-related protocols, including AHB, APB, and the AHB-to-APB bridge.
  • ▫️Verified designs using a UVM testbench through command-line mode.
  • ▫️Developed various test cases to achieve comprehensive design verification.
  • ▫️Generated and analyzed coverage reports.
Computer SimulationsSystemVerilogVLSI Design Verification

Education

JNTUA College of Engineering, Pulivendula

Bachelor of Technology - BTech — Electronics and communication engineering

Feb 2020Apr 2024

Viswasai Jr.College Nellore

Intermediate — M.P.C

Jul 2018Jan 2020

Dr.SRK E.M High School Nellore

Secondary School Education

Jun 2017Apr 2018

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