V

Vijendran Neethisekharan

Software Engineer

Bengaluru, Karnataka, India21 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in Front End Design and RTL Architecture.
Over 15 years of experience in IC Design and Verification.
Proficient in multiple hardware description languages.

Stackforce AI infers this person is a highly skilled engineer in ASIC and RTL design within the semiconductor industry.

Contact

Skills

Core Skills

Rtl DesignFront End Design

Other Skills

RTL CodingCoverage AnalysisSystemVerilogVerilogVHDLApplication-Specific Integrated Circuits (ASIC)ARMShell ScriptingLintCDCLECLow-power DesignUPFConformal Low PowerSynopsys Design Compiler

Experience

21 yrs 5 mos

Total Experience

4 yrs 3 mos

Average Tenure

8 yrs 2 mos

Current Experience

Qualcomm

2 roles

Senior Staff Engineer

Promoted

Nov 2022 – Present · 3 yrs 6 mos

RTL CodingRTL DesignFront End Design

Staff Engineer

Mar 2018 – Nov 2022 · 4 yrs 8 mos

RTL CodingRTL DesignFront End Design

Maxim integrated

Senior MTS, IC Design (Digital)

Jul 2014 – Mar 2018 · 3 yrs 8 mos · Bengaluru Area, India

RTL CodingRTL DesignFront End Design

C-dac r&d, bangalore

Senior Technical Officer (Scientist C Grade)

Mar 2008 – Jul 2014 · 6 yrs 4 mos · Bangalore

RTL CodingRTL DesignFront End Design

Tata elxsi

Senior Engineer

May 2007 – Mar 2008 · 10 mos · Bangalore

RTL CodingRTL DesignFront End Design

Cdac r&d, bangalore

Project Engineer

Dec 2004 – May 2007 · 2 yrs 5 mos · Bangalore

RTL CodingRTL DesignFront End Design

Education

Periyar University

Bachelor of Engineering - BE — Electronics and Communications Engineering

Jan 2000 – Jan 2004

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