Sakchi Sinha

Software Engineer

Bengaluru, Karnataka, India6 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in FPGA design and verification methodologies.
Filed 2 patents for innovative solutions.
Proficient in System Verilog and QuestaSim.

Stackforce AI infers this person is a specialist in FPGA design and verification within the semiconductor industry.

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Skills

Core Skills

Field-programmable Gate Arrays (fpga)Rtl DevelopmentFunctional VerificationDigital Rtl Design

Other Skills

LintCDCStatic Timing AnalysisApplication-Specific Integrated Circuits (ASIC)Universal Verification Methodology (UVM)Problem SolvingHardware EngineeringCommunicationCoverage AnalysisDesign ToolsSpecificationsRTL DesignInterpersonal CommunicationComputer-Aided Design (CAD)Timing

About

* FPGA Design Engineer * Skilled in IP development using System Verilog for high-speed serial protocols with timing closure and optimized performance * Experience in functional verification of on-chip protocols * Proficient in industry-standard tools, including Quartus, Vivado and QuestaSim. * Passionate about innovation, with 2 patents filed for novel solutions * Committed to advancing FPGA design and verification methodologies to drive next-generation tech solutions

Experience

Tektronix

4 roles

Senior FPGA Design Engineer

Oct 2025 – Present · 5 mos

FPGA Design Engineer

Promoted

Oct 2021 – Sep 2025 · 3 yrs 11 mos

RTL DevelopmentLintCDCField-Programmable Gate Arrays (FPGA)Static Timing AnalysisApplication-Specific Integrated Circuits (ASIC)+14

Software Design Engineer

Jul 2020 – Sep 2021 · 1 yr 2 mos

Intern

Jan 2020 – Jun 2020 · 5 mos

Mentor graphics

Functional Verification Engineer

Jun 2019 – Jul 2019 · 1 mo · Bengaluru, Karnataka, India

Functional Verification of LC3 Microcontroller using System Verilog in QuestaSim
Functional Verification of Universal Memory Controller using System Verilog in QuestaSim
Digital RTL Design implementation of Interrupt Controller using Verilog HDL in QuestaSim

Problem SolvingInterpersonal CommunicationTimingFunctional Verification