Vishwanath Hiremath

Software Engineer

Karnataka, India11 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL Design and Verification of digital IPs.
Proficient in Verilog and System Verilog for RTL implementation.
Strong educational background from IIT Gandhinagar.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on Digital IC Design.

Contact

Skills

Core Skills

Semiconductor EngineeringDigital Ic Design

Other Skills

TimingDigital ElectronicsMicrocontrollersCSystem VerilogVerilogLogic SynthesisFront-end DesignEmbedded SystemsAnalog CircuitsMicrosoft ExcelUniversal Verification Methodology (UVM)PythonCircuit DesignMicroprocessors

About

Experienced professional in RTL Design and Verification of digital IP's. Competent in Architecture design, RTL implementation using Verilog, Verification using System Verilog and well versed with tools like Synopsys VCS simulator, Design Compiler, Power Artist, Xilinx Vivado. Strong engineering professional with a Master’s Degree focused in Microelectronics and VLSI from Indian Institute of Technology Gandhinagar

Experience

11 yrs 7 mos

Total Experience

2 yrs 2 mos

Average Tenure

5 yrs 6 mos

Current Experience

Samsung semiconductor india

2 roles

Senior Staff Engineer

Promoted

Mar 2023 – Present · 3 yrs 2 mos

Semiconductor EngineeringDigital IC Design

Staff Engineer

Nov 2020 – Mar 2023 · 2 yrs 4 mos

RTL Design Engineer

Semiconductor EngineeringDigital IC Design

Mediatek

Senior Engineer

Jul 2018 – Oct 2020 · 2 yrs 3 mos · Bengaluru Area, India

Worked as a Senior Engineer on 5G modem projects and AHB/AXI IP's

Digital IC Design

Xilinx

Intern

Jan 2018 – Jun 2018 · 5 mos · Hyderabad Area, India

Performance benchmarking for CCIX over PCIe
HDMI and SDI TRD

Mentor graphics

Functional Verification Trainee

Jun 2017 – Jul 2017 · 1 mo · Bangalore

Selected among 30 students across India for the Mentor Graphics Higher Education Program (2017)
7 week intensive training on Functional Verification using SystemVerilog
Course Adapted from Graduate ASIC Verification course of North Carolina State University (ECE 745)
Training modules ----
Developing layered, object oriented testbenches in SV
Constrained randomization, Assertion based Verification, Coverage driven verification
Introduction to Universal Verification Methodology (UVM).

Vlsi master's student at iit gandhinagar

Masters Student

Aug 2016 – Jul 2018 · 1 yr 11 mos · Gujarat, India

Indian institute of technology gandhinagar

Graduate Teaching Assistant

Aug 2016 – Dec 2017 · 1 yr 4 mos · Gandhinagar

Worked as Teaching assistant and project guide in the Analog circuits lab for a group of 4 3rd year Undergraduate students (Aug 2016 - Dec 2016).
Worked as Teaching assistant and project guide in the Digital circuits lab for a group of 8 2nd year Undergraduate students (Jan 2017 - Apr 2017).
Working as Teaching assistant and project guide in the Digital circuits course for 2nd year undergraduate students. (Aug 2017 - Present)

Bosch india

Software Engineer

Jul 2014 – Jun 2016 · 1 yr 11 mos · Bengaluru Area, India

Product development in automotive electronics and software development for Electronic control units of passenger cars of Hyundai and Kia.
Good Knowledge of various Communication Protocols – I2C, CAN, LIN.
Unit testing and system testing using INCA on Lab cars and vehicle with good debugging skills.
Hands on experience working with Infineon Tri core processors (TC1767, TC1793).
Fair knowledge in Product Development and engineering.
Received timely appreciation from customer unit at South Korea for meeting work expectations.
Scored an employee PRED rating of 1.6 out of 2, during my second year at Bosch.