SHANTANU JAWALE

Software Engineer

Bengaluru, Karnataka, India11 yrs 1 mo experience

Highly Stable

Key Highlights

Expertise in CPU core design and branch prediction algorithms.
Proficient in RTL design using Verilog-HDL and System-Verilog.
Strong background in low power intent design for SoCs.

Stackforce AI infers this person is a highly skilled VLSI design engineer with extensive experience in CPU architecture and mixed signal design.

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Skills

Other Skills

ASICAlteraAltera QuartusAnalog Circuit DesignApplication-Specific Integrated Circuits (ASIC)C++CCDCPFCadence VirtuosoCadence Virtuoso Layout EditorDesign Verification TestingDigital Circuit DesignDigital Signal ProcessingElectronicsFPGA

About

- Mtech + ~11 year Experience on IP level Designs and Subsystem Design, Mixed signal Design for various SoCs. Good knowledge in ARM/X86 CPU architecture, Instruction Fetch Unit (L1-Icache), Branch Prediction Algorithms(perceptron based neural algorithm), RAS, Floating point ,Vector Processing(SIMD) . - Expertise in RTL Design using Verilog-HDL, Sytem-Verilog. - Worked on Low power intent design (CPF/UPF/CLP) - Self motivated, very quick learner and a good team member. email : shantanujawale@gmail.com

Experience

Amd

Member of Technical Staff

Mar 2024 – Present · 2 yrs · Bengaluru, Karnataka, India

Working on CPU Core Design team
L1 I-Cache unit & Branch Prediction Unit

Qualcomm

4 roles

Staff Engineer

Dec 2022 – Feb 2024 · 1 yr 2 mos

• Worked on a next-generation compute & Automotive chip based on the Nuvia CPU

Senior Lead Engineer

Dec 2020 – Nov 2022 · 1 yr 11 mos

CPU core Design
Worked on Floating point unit (FPU) & Vector Processing Unit (SIMD)

Senior Design Engineer

Dec 2018 – Nov 2020 · 1 yr 11 mos

CPU core deign
Worked on Branch Prediction Unit of In order core
Designed and implemented a 2stage perceptron predictor (Neural Network based) as backing branch
predictor and a Mutli-component target predictor consisting of Branch type predictor, Direct branch
target buffer, Indirect branch target buffer, and Return Address Stack.

Design Engineer

Dec 2016 – Nov 2018 · 1 yr 11 mos

CPU core Design
Worked on Instruction Fetch Unit (IFU) of In order core (L1-Icache, IQ, I-Buffer, Miss Buffer)
CPU Sub System Design
Snapdragon 8CX compute chip

Cadence design systems

Design Engineer

Jun 2015 – Dec 2016 · 1 yr 6 mos · Greater Bengaluru Area

As a RTL design engineer have done Digital Logic Design of AMS IP's PLL,ADC, Analog TestChip etc
RTL coding, Simulation, Synthesis , Logic equivalence checking (LEC).
Responsible for creating timing constraints(SDC) for PLL.
Responsible for setting up the RDF flow for project.
Quality checks using SpyGlass LINT,SDC and CDC check. , Experience in various Cadence tools.
Responsible for Verification of design from front end side at different design cycles using test bench (Verilog-HDL), Gate-level simulation(GLS),Zero delay simulation
Automation for .libs using PERL
.libs creation of ANALOG IP's and checks using PT,ECSM,crossfire,RC,LC,LP.
UPF,CPF for Analog Test chip and verified using CLP.
Developed verilog behavioral model for Analog Test chip.
Developed IPXACT(xml) for register description of ADC.

Vellore institute of technology

Technical Research Assistant

Oct 2014 – May 2015 · 7 mos · India

Design of SAR ADC for Bio-medical Application
In this thesis first focus on functionality SAR structure . It also focus additionally on low power comparator using Inverter based topology architecture which is in voltage mode logic so that silicon area and power requirement can be reduce because comparator is one of the main building block and capacitor swapping method for reduction of capacitor mismatch in DAC. On the basis of this study a SAR ADC for low power in 90nm technology node is analyzed using parameters like SNR,SFDR,FOM, INL, DNL, ENOB etc.