ARSHAD MIR — Director of Engineering
24+ years of work experience in Design/Development and Test validation/characterization. • Reach Pre-SOC ( FPGA Platforms) and Post-SOC validation milestones on time in full by keeping visibility, understanding and control over full cycle. • SOC Validation Test Cases as low level software development in C language, functional and Stress Testing under PVT. • Lead Customer returns, Cross team investigation and proposing acceptable workarounds. • Complete VVR, ICOS Review, Validation Test Plan and strategy for better Coverage. • Drive and participate in IOT( Interoperability) programs with partners. • Characterization of High Speed Interfaces( MIPI MPHY,PCIe) • Complete hardware cycle of developing systems starting from the requirement from Product Manager to diagnosing and fixing issues reported from the field. • Device Chipset Selection, Quote Negotiations with Silicon Vendors and BOM Cost. • Hardware Design and Development of Access Modules for MSAN and IPDSLAM Platforms. • Complete Prototype Board Bring up and Responsible for Fixing Hardware defects. • Interface with Factory and Sourcing Teams for Prepilot and Pilot runs for New Designs Transfer of Technology and Fixing of ECRs, and implementation of Change Notifications of the components. • Interface with Field support team to resolve Field defects for legacy Hardware at Customer sites globally ( FXS/E1/SHTM). • Active Role in Drafting PCB Stackup and Layout Guidelines for the Layout Team and reviewing of the PCB Board file. • Interface with Compliance Teams (EMI/EMC, Mechanical/thermal) to carry out CE of the Product. • Complete Design documentation ( HDD, UTP, FTP) • Active Member on AGILE Web, Always looking in the areas (Legacy Hardware) where Cost of the Hardware can be reduced with minimal software impact. • Significant Role during the transitioning to ROHS Modules. • Responsible for doing Hardware Design schematic Reviews Globally. • Responsible for FPGA/CPLD Development and functional TEST Validation.
Stackforce AI infers this person is a Telecommunications Hardware Engineer with extensive experience in SOC validation and high-speed interface design.
Location: Bengaluru, Karnataka, India
Experience: 23 yrs 9 mos
Skills
- Soc Validation
- Hardware Validation
- Hardware Architecture
- Fpga Development
- Hardware Design
- Validation Testing
Career Highlights
- Over 24 years of experience in design and validation.
- Expertise in SOC validation and high-speed interface characterization.
- Proven track record in leading engineering teams at Intel.
Work Experience
Intel Corporation
Director Of Engineering -Lead Validation steering Teams (5 yrs 1 mo)
Senior Manager Engineering- SOC validation (3 yrs 3 mos)
Engineering manager & Technical Lead (3 yrs 1 mo)
Ericsson
Sr. TECH LEAD (1 yr 3 mos)
ST ERICSSON INDIA PVT LTD
TECHNICAL GROUP LEAD (1 yr 5 mos)
TECHNICAL LEADER (10 mos)
UTStarcom
Senior Design Engineer Research and Development (6 yrs 1 mo)
HFCL
Design ENGINEER( MEMBER TECH STAFF) (2 yrs 9 mos)
Education
GRADUATE IN ENGINEERING at SRINAGAR
